High-performance approximate half and full adder cells using NAND logic gate

Abstract

In this letter, NAND-based approximate half adder (NHAx) and full adder (NFAx) cells are proposed for low power approximate adders. NHAx and NFAx architectures are built using NAND logic gate which has a minimal normalized gate delay among all the CMOS based integrated circuit digital logic family; therefore, an improvement of 29% in the critical path delay is achieved. For the performance evaluation, 8-bit ripple carry adder (RCA) is then built using proposed cells. RCA-NFAx shows a good power-efficiency trade-off when both power delay product and error metric NMED are considered with reference to the previous approximate 1-bit FA based RCA designs.