IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus
Takefumi YoshikawaTatsuya IwataJunji ShibazakiSho MurogaHiroaki Ikeda
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2020 Volume 17 Issue 10 Pages 20200112

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Abstract

This paper describes theoretical approach and proposed scheme of wide data bus architecture using charge-recycling and stacked I/O for signal transmission via TSV (Through Silicon Via). This data bus is assumed for vertical stacked chips of 3D integration. This theoretical approach is based on probability calculation for data stream on pure random pattern. Through the calculation, power reduction ratio to normal data bus (non-charge recycling) is clarified in given conditions for power estimation in early design stage. The proposed scheme for data and clock transmission adopts Local Voltage Stabilizer (LVS) and compact level shifter for capacitor area and clock power reduction. Simulation results show that the proposed 2 story data bus architectures of 64bits (32×2) and 128bits (64×2) achieve competitive power efficiency (0.160pJ/bit) with smaller size (44% to prior work) and normal operation voltage (1V). These achievements are in dense TSVs (40μm pitch), standard 65nm process technology and PRBS9 data stream.

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© 2020 by The Institute of Electronics, Information and Communication Engineers
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