The development of DRAM cannot meet the low power requirement of IoT applications due to the high refresh power. As one of new non-volatile memory, STT-MRAM has extremely low static power, high read performance and high endurance. In this paper, we build a hybrid DRAM and STT-MRAM main memory to reduce energy. Considering STT-MRAM’s high write power and high write latency, we propose a fast cacheline-based data replacement to reduce write operations of STT-MRAM. The results show that the hybrid DRAM and STT-MRAM main memory can provide comparable performance to DRAM, with an average 32% reduction in main memory energy.

This paper models and analyzes the power efficiency of wireless power transfer systems with arbitrary load impedances using passive two-port network parameters. In this formulation, two novel indices--the load resistance optimization factor and the load reactance optimization factor--are defined and introduced to indicate the deviation of the load resistance and load reactance from their optimal values. It is shown that the power efficiency of these systems can be formulated using only their k-Q product and the defined load optimization factors. Additionally, we show that the ratio of efficiency to maximum available efficiency can be characterized with one single complex factor. The proposed approach helps the quantitive interpretation of the efficiency deterioration by the difference between the load impedance and its optimal value.

The non-ideal factors and error sources of segmented DAC for multi-channel large array CMOS image sensor are given. An improved precise segmented DAC using adaptive switching technology is proposed. This scheme has been verified on a 50mm×50mm large array CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The measurement results show that the DNL of DAC can be reduced from 33 LSBs of traditional structure to within 0.5LSB, and the large array sensor chip reaches a high intrinsic dynamic range of 75dB, a low FPN of 0.06%, and a low photo response non-uniformity of 1.5% respectively. Finally, a good raw image is taken by the prototype sensor.

In this paper, a 16-bit 8-MS/s successive approximation register analog-to-digital converter (SAR ADC) with a foreground calibration technique is proposed. A nonbinary searching algorithm is adopted to speed up the conversion rate and overcome the incomplete settling of the reference voltage. A foreground calibration method with low-cost circuitry is implemented to detect the mismatch of the capacitor digital-to-analog converter in calibration mode and compensate for the output code in conversion mode. The simulation results show that the peak signal-to-noise and distortion (SNDR) and spurious free dynamic range (SFDR) are improved from 69.98 dB to 91.39 dB and 73.94 dB to 99.41 dB, respectively. Moreover, the proposed ADC uses a hybrid-charge-supply power structure. The sampling circuit operates at 3.3 V to maintain a wide dynamic range, the logic circuit operates at 1.2 V to decrease the conversion time and power consumption, and the total power consumption is 45 mW at 8 MS/s.

Asymmetry of differential transmission lines over a meshed ground plane causes differential skew, which leads to signal integrity issues. We measured to evaluate how the angle between the differential transmission lines and meshed ground (the rotation angle) affected differential skew. We also investigated the effect of the lines’ position on characteristic impedance and the feasibility of high-density layout of the differential transmission lines, including the bend structure. We found that the differential skew and characteristic impedance are not significantly affected by the position of the differential transmission lines and meshed ground when the rotation angle is set to 30°, a relatively small value. Measurements showed that our design is effective.

This study uses a pulsed laser to investigate the sensitivity of a sequential logic circuit to a Single-Event-Upset (SEU) under different supply voltages, clock frequencies, and circuit architectures. The experimented sequential logic circuit is a D flip-flop chain manufactured in 65-nm bulk CMOS technology. The results indicate that as the voltage decreases, the SEU sensibility of the circuit increases, and in particular at low voltage ranges, it increases significantly. Additionally, the effect of clock frequency on the sensitivity of the sequential logic circuit is mainly related to the propagation of Single-Event-Transients (SETs) that are generated in combinational logic circuits. It was also found that, the Set-architecture circuit is more sensitive to SEUs during the data “0” test, while the Reset-architecture circuit is more sensitive to SEUs during the data “1” test. In addition, the failure mechanisms of SEU induced by Set-structure and Reset-structure are revealed using SPICE simulations.

In this paper, an 8-channel 16 bit 200 kS/s successive approximation register analog-to-digital converter (SAR ADC) realized in 130 nm SOI CMOS technology is presented. A capacitor-resistor hybrid digital-to-analog converter (DAC) is adopted in this design to avoid the bulky capacitor array. In addition, an on-chip self-calibration technique is proposed to calibrate the mismatch of the capacitors in the DAC. To simplify the calibration logic of the resistor DAC, an auxiliary capacitor is added in the capacitor DAC to replace the resistor DAC for calibration. Moreover, the added auxiliary capacitor can also be utilized to correct the errors caused by the incomplete settling of reference voltage during the conversion. The measured results show that signal-to-noise-and-distortion-ration (SNDR) and spurious-free-dynamic-range (SFDR) compared with it without calibration are improved from 76.51 dB to 85.82 dB and 80.84 dB to 95.14 dB, respectively. The proposed ADC occupies an active area of 0.966 mm² and consumes a total power of 3.1 mW.

This paper describes theoretical approach and proposed scheme of wide data bus architecture using charge-recycling and stacked I/O for signal transmission via TSV (Through Silicon Via). This data bus is assumed for vertical stacked chips of 3D integration. This theoretical approach is based on probability calculation for data stream on pure random pattern. Through the calculation, power reduction ratio to normal data bus (non-charge recycling) is clarified in given conditions for power estimation in early design stage. The proposed scheme for data and clock transmission adopts Local Voltage Stabilizer (LVS) and compact level shifter for capacitor area and clock power reduction. Simulation results show that the proposed 2 story data bus architectures of 64bits (32×2) and 128bits (64×2) achieve competitive power efficiency (0.160pJ/bit) with smaller size (44% to prior work) and normal operation voltage (1V). These achievements are in dense TSVs (40μm pitch), standard 65nm process technology and PRBS9 data stream.

This paper presents a compact implementation of a switch-linear hybrid envelope tracking supply modulator (HETSM). By combining transconductance-enhanced method and nonlinear current mirror technique in the operational transconductance amplifiers (OTAs), the proposed linear amplifier (LA) which utilizes the OTAs with class AB output stage achieves improved gain bandwidth and boosted slew-rate without increasing quiescent current. A good stability can also be attained without using any on-chip and off-chip compensation capacitors. The proposed LA facilitates the HETSM to achieve fast tracking with reduced chip area. An HETSM using the proposed LA in parallel with a hysteretic buck converter has been fabricated in 0.18-µm 1.8/5 V CMOS process with 1.24 mm² die size. The measured results show that the HETSM is able to track a 10 MHz LTE signal accurately with less than 1.5% output error, achieving the maximum efficiency of 83% at 1W output power with 5 Ω resistive load. The HETSM can accommodate the variation of loading from 5 Ω to 20 Ω.