A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication

Abstract

A new all-digital multiplying delay-locked loop (MDLL) based frequency multiplier architecture with a high frequency multiplication factor N of 256 is presented. The proposed MDLL utilizes a dithering jitter reduction scheme based on a delta-sigma modulation to achieve a low deterministic jitter and a large N factor. Additionally, a new stochastic phase detector is proposed to reduce static phase offset and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed all-digital MDLL generates 2.4-GHz output clock and achieves a peak-to-peak jitter of 6.47 ps with N=256. It occupies an active area of 0.032 mm² and achieves a power efficiency of 0.875 mW/GHz.