IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 17 , Issue 19
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LETTER
  • Tingting Shi, Sizheng Chen, Na Yan, Hao Min
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 19 Pages 20200281
    Published: October 10, 2020
    Released: October 10, 2020
    [Advance publication] Released: September 23, 2020
    JOURNAL FREE ACCESS

    Wideband receiver used in IoT applications operating at sub-GHz suffers from strong interferes. This paper presents a blocker-resilient wideband receiver architecture for NB-IoT applications. By exploiting the impedance mapping characteristic of N-Path filter and a low noise amplifier with negative feedback, a high-order filtering characteristics of baseband is mapped to RF input so as to implement wideband impedance matching and blocker suppression. To further improve the out-of-band linearity, a dual mixer structure is employed to cancel the out-of-band blockers before the TIA. Measurements show the RX out-of-band IIP3 is +17.6 dBm, while in-band IIP3 is -13 dBm.

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  • Dongjun Park, Jongsun Kim
    Type: LETTER
    Subject area: Integrated circuits
    2020 Volume 17 Issue 19 Pages 20200296
    Published: October 10, 2020
    Released: October 10, 2020
    [Advance publication] Released: September 23, 2020
    JOURNAL FREE ACCESS

    A new all-digital multiplying delay-locked loop (MDLL) based frequency multiplier architecture with a high frequency multiplication factor N of 256 is presented. The proposed MDLL utilizes a dithering jitter reduction scheme based on a delta-sigma modulation to achieve a low deterministic jitter and a large N factor. Additionally, a new stochastic phase detector is proposed to reduce static phase offset and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed all-digital MDLL generates 2.4-GHz output clock and achieves a peak-to-peak jitter of 6.47 ps with N=256. It occupies an active area of 0.032 mm2 and achieves a power efficiency of 0.875 mW/GHz.

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