Bit-serial systolic accelerator design for convolution operations in convolutional neural networks

抄録

The accuracy of Convolutional Neural Networks (CNNs) has exceeded the human level in many fields, but the high computation complexity is one of the main challenges for CNNs applied in the mobile or embedded devices. In this paper, we provide a hardware accelerator scheme for the convolution operations in CNNs, which adopts the bit-serial systolic architecture. Implementation results show that the proposed scheme can reduce the area by about 64%, increase the maximum frequency by about 4.4 times and increase the hardware efficiency by about 1.2 times compared with the state-of-the-art Eyeriss architecture.