A self-clocked binary-seaching digital low-dropout regulator with fast transient response

Abstract

A self-clocked binary-searching (SCBS) digital low-dropout (DLDO) regulator with fast transient response is proposed. The SCBS controller employed in the DLDO achieves fast transient response and eliminates the need for an external high-speed clock. A transient enhancement unit (TEU) is proposed to reduce the undershoot of the output voltage. The proposed DLDO is simulated in a 40-nm CMOS process with an active area of 0.015 mm². The simulation results show that with a 15.5mA/2ns load step, it shows a setting time of 28 ns with a voltage undershoot of 93 mV, and it achieves a peak current efficiency of 99.87% by consuming a 19.4-µA quiescent current. Thus, the resulting FOM₁ is 0.379 ps and FOM₂ is 5 ps.