An air-core transformer is a suitable device for megahertz-class power converters. This letter presents an equivalent circuit of a fabricated interleaved air-core toroidal transformer. In order to determine the modeling parameter of the transformer, the electrical characteristics are discussed on the basis of the frequency responses measured from 0.1 to 110MHz. As a result, it is found that the fabricated transformer is dominated by the mutual capacitance in addition to the self- and mutual inductance. The proposed equivalent circuit is distributed parameter model. This is derived from analogy with the coupled transmission lines. The equivalent circuit shows an excellent agreement with the experiment. These results conclude that the importance of the mutual capacitance to be implemented as a distributed parameter.
Triple modular redundancy (TMR) is widely used in FPGA/ASIC circuits to protect circuits against single event upsets (SEUs). However, because of the interference of metastability on signal transmission across clock domains, the TMR circuits’ capability against SEUs is reduced greatly. In order to solve this problem, a cross-clock transmission solution which could be applied in TMR circuits are presented. In addition, simulation-based verification which combined protocol assertions, metastable injection and forced inversion is proposed to succeed in verifying the availability of the solution based on TMR circuits.
A self-clocked binary-searching (SCBS) digital low-dropout (DLDO) regulator with fast transient response is proposed. The SCBS controller employed in the DLDO achieves fast transient response and eliminates the need for an external high-speed clock. A transient enhancement unit (TEU) is proposed to reduce the undershoot of the output voltage. The proposed DLDO is simulated in a 40-nm CMOS process with an active area of 0.015 mm2. The simulation results show that with a 15.5mA/2ns load step, it shows a setting time of 28 ns with a voltage undershoot of 93 mV, and it achieves a peak current efficiency of 99.87% by consuming a 19.4-µA quiescent current. Thus, the resulting FOM1 is 0.379 ps and FOM2 is 5 ps.
In this letter, we present a new structure of spin-orbit torque magnetic random access memory (SOT-MRAM) for area optimization. Based on the observation of SOT-MRAM layout that the metal line can be added in the horizontal direction without increasing the cell area, the proposed design optimizes the metal line routing direction as well as biasing conditions for read and write operations. Implemented with a 45-nm CMOS technology, the proposed design achieves cell area reduction of 42% (23%) compared with the conventional SOT-MRAM (STT-MRAM). The proposed design achieves 6.26x lower write power than STT-MRAM by taking advantage of high spin current injection efficiency. Also, owing to separate read and write current paths, the proposed design can optimize each path independently, resulting in 7.69x lower read power and 1.88x higher read-disturb margin in comparison to STT-MRAM that has a common path for read and write operations.
A linearly polarized slot antenna integrated with solar cells is presented. The proposed antenna operates at the center frequency of 1.575 GHz for the global navigation satellite systems. 40 solar cells are adopted for the radiation structure and 4 slots are formed by these solar cells, which can not only be used for wireless communication but also generate DC energy via the photoelectric effect. The proposed design has achieved a relative bandwidth of 19.9% from 1.45 GHz to 1.77 GHz. Bidirectional radiation performance has been realized and the measured gain at 1.575 GHz is 6.6 dBi.