A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

Abstract

A synchronous driving approach for stitching CMOS image sensor is proposed. Dual terminal signal line driver structure must be considered in the design of row control for high definition CMOS image sensor pixel array. However, as the size of the array increases further, the traditional synchronization technologies such as clock tree cannot be applied because of the stitching technology. Furthermore, this invalidity will cause DC shoot through and dead line. Based on the adaptive delay phase-locked loop, dual terminal signal line driver with highly efficient synchronization for pixel array is realized in a single die CMOS image sensor with 225M pixels and large area of 120 × 120 mm². The comparison results show that the timing matching improves by two orders of magnitude, and the consistency reaches 99.95%.