A synchronous driving approach for stitching CMOS image sensor is proposed. Dual terminal signal line driver structure must be considered in the design of row control for high definition CMOS image sensor pixel array. However, as the size of the array increases further, the traditional synchronization technologies such as clock tree cannot be applied because of the stitching technology. Furthermore, this invalidity will cause DC shoot through and dead line. Based on the adaptive delay phase-locked loop, dual terminal signal line driver with highly efficient synchronization for pixel array is realized in a single die CMOS image sensor with 225M pixels and large area of 120 × 120 mm². The comparison results show that the timing matching improves by two orders of magnitude, and the consistency reaches 99.95%.

Electrical field induced conductive switching materials are novel nonlinear materials. They can show an abrupt reduction of resistivity when the external electrical field strength exceeds a predefined threshold, and the materials will switch from insulated state to conductive state. In this letter, a novel time-domain response characteristics test method of conductive switching materials induced by electromagnetic pulse field was proposed based on the parallel micro-strip principle. In the experiments, the test principle was analyzed by the equivalent circuit model and micro-strip principle, and the evaluation method of resistivity, response time and field strength threshold value of the materials under tested was also given. The theoretical results of the typical conductive switching material agree well with the experimental data.

In this paper, a calibration method aiming at the timing mismatch existing in the TIADC (Time-Interleaved Analog-to-Digital Converter) is proposed. Monotonicity detecting of the sampled data is employed to estimate the mismatch error, in which only additive operation is involved. Besides that, an improved Taylor expansion method is used to compensate the mismatch error. The processes of the estimation and the compensation are designed to constitute an adaptive loop, so that the calibration can be run in real-time. Compared with other approaches, this method consumes less hardware resources and has a good calibration result.

For the purpose of reducing the peripheral crosstalk occur in the edge pixel, we illustrated a method to test and quantify the intensity of this crosstalk, and setup a model combining the opposite incident light and color construction. With the aid of the method and model, we conducted many experiments to analyze and compare the improvement measures, finding that the increase of pixel edge to package edge distance, sealing glass thinning and black photoresist coating around edge are all effective to reduce the peripheral crosstalk. Moreover, considering the effect and cost, the sealing glass thinning is the relatively best measure.

A wideband low-jitter phase-locked loop (PLL) is proposed to provide high performance clocks for the transceivers. The ring voltage-controlled oscillator (Ring-VCO) is a key component of a PLL, which directly determine the out-band phase noise and output frequency range of the PLL. Therefore, a low phase noise two-stage Ring-VCO with a novel delay cell is proposed to help achieve a wideband low-jitter PLL. An accumulation-mode MOS (AMOS) varactor pair is adopted in the delay cell to improve the fine tuning linearity. Moreover, an additional AMOS varactor pair is employed to reduce the VCO gain variation in the coarse tuning process and enhance the tolerance in temperature and voltage variations. Implemented in a conventional TSMC 180 nm CMOS process, the proposed Ring-VCO can tune from 0.73 to 1.92 GHz and the worst-case phase noise at 1 MHz offset is −102 dBc/Hz. The output frequency range of the proposed PLL is 0.06–1.92 GHz and the RMS jitter is less than 3.8 ps over the whole working band.

A high frequency and high efficiency DC-DC converter with sensorless adaptive-sizing technique is proposed. Instead of conventional adaptive-sizing technique with current sensor, the proposed converter estimates the load current according to the output voltage of error amplifier for switch scaling. The elimination of current sensor reduces power consumption, thus improving efficiency further. This design is validated through simulation in a 0.18 µm CMOS process. At switching frequency of 150 MHz and light-load of 20 mA, the proposed converter achieves a high efficiency of 82.4%, while it is 73.7% with conventional adaptive-sizing technique, and 62.4% without adaptive-sizing technique.

In this letter, we propose a method for optimizing the thermal placement of heat and non-heat generating electronic components on a printed circuit board (PCB). Use a genetic algorithm to optimize the maximum temperature of the PCB and the total wire length between components. In the case that chips stacked in 3D ICs are reconfigurable, each chip construction of 3D ICs is also changed simultaneously. The temperature of each component is obtained by circuit simulation using a simple thermal circuit model. The experimental results demonstrate that the placement of components can be optimized well for lowering the maximum temperature with shorter wire lengths.

This letter details a novel floating-bulk transistor technique for low-voltage design. The approach is derived from two previous well-known techniques: bulk-driven and quasi floating-gate. The floating-bulk technique uses an input capacitive coupling through a floating bulk of a PMOS allowing modulation of the drain current. A fabricated common-source amplifier was tested on CMOS 0.5 µm technology and the feasibility of the proposal was demonstrated.