Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data

Yongsheng Yin; Kangkang Sun; Hongmei Chen; Xiaolei Wang; Lu Liu; Honghui Deng; Xu Meng; Kun Li; Zhongfeng Wang

doi:10.1587/elex.17.20190699

LETTER

Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data

Yongsheng Yin, Kangkang Sun, Hongmei Chen, Xiaolei Wang, Lu Liu, Honghui Deng, Xu Meng, Kun Li, Zhongfeng Wang

Author information

Yongsheng Yin
Institute of VLSI Design, Hefei University of Technology
Kangkang Sun
Institute of VLSI Design, Hefei University of Technology
Hongmei Chen
Institute of VLSI Design, Hefei University of Technology
Xiaolei Wang
Institute of VLSI Design, Hefei University of Technology
Lu Liu
Science and Technology on Analog Integrated Circuit Laboratory
Honghui Deng
Institute of VLSI Design, Hefei University of Technology
Xu Meng
Institute of VLSI Design, Hefei University of Technology
Kun Li
China Key System & Integrated Circuit Co., Ltd.
Zhongfeng Wang
School of Electronic Science and Engineering, Nanjing University

Keywords: monotonicity detecting, timing mismatch, sign judgment, Taylor expansion

JOURNAL FREE ACCESS

2020 Volume 17 Issue 3 Pages 20190699

DOI https://doi.org/10.1587/elex.17.20190699

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Abstract

In this paper, a calibration method aiming at the timing mismatch existing in the TIADC (Time-Interleaved Analog-to-Digital Converter) is proposed. Monotonicity detecting of the sampled data is employed to estimate the mismatch error, in which only additive operation is involved. Besides that, an improved Taylor expansion method is used to compensate the mismatch error. The processes of the estimation and the compensation are designed to constitute an adaptive loop, so that the calibration can be run in real-time. Compared with other approaches, this method consumes less hardware resources and has a good calibration result.

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