A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

抄録

In this paper, a high-speed low-power SAR ADC is designed. In this prototype, an improved switching scheme combined with the optimized attenuation capacitor architecture is proposed, showing more power efficiency and is more suitable for high-speed data converters. Meanwhile, an improved synchronous timing strategy is employed, achieving flexible time allocation of DAC settling and comparison in each bit-cycle. In addition, a two-stage non-tail-current-source and single-phase-clock comparator is proposed with more power-efficiency and compatible resolving time. The prototype ADC is fabricated in a 40nm CMOS technology and occupies an active area of 0.04mm². An SNDR of 57.18dB and an SFDR of 75.29dB are achieved with the Nyquist rate input at a sampling rate of 160MS/s, consuming 1.3mW at 1.1V supply voltage.