A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Abstract

This paper describes quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with summer reduction technique for high-speed serial communication in a 65nm CMOS technology. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer. Therefore, the proposed DFE reduces power consumption significantly because summer dissipates a lot of power. The DFE that is verified by pre-layout simulations achieved 0.69 unit-interval (UI) eye-opening. The proposed DFE that is designed with a 65-nm technology operates at 28Gb/s and occupies 0.023mm². Finally, the power efficiency of the proposed DFE is 0.88-pJ/bit.