This paper describes quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with summer reduction technique for high-speed serial communication in a 65nm CMOS technology. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer. Therefore, the proposed DFE reduces power consumption significantly because summer dissipates a lot of power. The DFE that is verified by pre-layout simulations achieved 0.69 unit-interval (UI) eye-opening. The proposed DFE that is designed with a 65-nm technology operates at 28Gb/s and occupies 0.023mm2. Finally, the power efficiency of the proposed DFE is 0.88-pJ/bit.
In this paper, we present a cochlea model whose nonlinear dynamics are described by an asynchronous cellular automaton. Our proposed model is demonstrated to enable the reproduction of two-tone distortion products. The proposed model is implemented on a field-programmable gate array (FPGA). It is subsequently demonstrated that our proposed model can be implemented using fewer hardware resources than a conventional cochlea model, which is a Hopf-type cochlea model, implemented on a digital signal processor performing a numerical integration.
Aimed at the emerging on-chip three-dimensional through-silicon vias (TSVs)-based inductor, the formula for the DC inductance is proposed. And then, based on this formula and the equivalent circuit model analytical models of AC inductance and quality factor are proposed considering frequency effect. Finally, the TSV-based inductors are fabricated and measured. It is shown that the reported results match very well with each other.