2021 Volume 18 Issue 20 Pages 20210309
An asynchronous Advanced Encryption Standard (AES) cryptographic processor for low-area and side-channel attack (SCA) resistant applications is introduced. To reduce the area and power, two Substituting Byte blocks (S-Boxes) are reused in key expansion and the data encryption module, respectively. To mitigate SCA, we adopt asynchronous dual-rail logic with dual-rail balanced logic and new dual-rail spacer latch. Common and Machine learning (ML) SCA simulations are performed to validate SCA resistance. To the best of our knowledge, we are the first ones to perform the ML SCA evaluations on asynchronous AES. Simulation results with 200K power traces demonstrate that our asynchronous AES is immune to the attacks. Our proposed asynchronous AES occupies an area of 0.016mm2 in TSMC 28nm technology and consumes 1nJ per encryption at a supply voltage of 0.9V.