Using multiphase permanent magnet synchronous generators (PMSG) is able to strengthen whole reliabilities of the tidal stream energy systems. Even so, advanced fault-tolerant control designs are also needed for a further enhancement of multiphase PMSG integrated tidal stream turbine under harsh sea water environments. Thus, extended state observers are used to develop a fault-tolerant control strategy towards a trapezoidal five-phase PMSG incorporated tidal stream application. This FTC strategy considers open circuit of a phase and a switch in the five-phase PMSG and its connected converter. To attenuate influences due to these faults, a dual-loop compensation mechanism is performed via extended state observers. System adaptation to swell effects of the tidal stream and feasibility of the proposed FTC strategy are verified through a 1.5 MW simulation setup.

A compact model of the biased dual-gate GaAs pHEMT device is proposed. The biased dual-gate pHEMT is considered as one macro unit to simplify the model and facilitate simulation. We derive the model based on analytical formulation and represent it with a simplified circuit containing only eight elements. The extrinsic elements are extracted using improved open-short method with a larger frequency range than traditional method. The simulated S-parameters based on the proposed model agree with the measured results well up to 40GHz for 0.25um dual-gate GaAs pHEMT devices. In addition, the large-signal model is constructed with a new empirical drain current model. A 2.4GHz power amplifier (PA) is designed using the proposed model, and the measurement results agree well with the simulation.

In this article, the embedded fan-out wafer-level packaging (FO-WLP) for 2-D ultrasonic transducer array with individual electrical connection is proposed. The finite element analysis (FEA) was employed to analyze effects of the package on ultrasonic transducers. The layout of the package was designed based on single-element FEA models. The impedance characteristic of the encapsulated array was measured. The model of encapsulated array was established. The simulation and measured results of the encapsulated array show that the effective electromechanical coupling coefficient is remarkable affected by redistribution layers (RDLs) and passivation layers (PLs).

An asynchronous Advanced Encryption Standard (AES) cryptographic processor for low-area and side-channel attack (SCA) resistant applications is introduced. To reduce the area and power, two Substituting Byte blocks (S-Boxes) are reused in key expansion and the data encryption module, respectively. To mitigate SCA, we adopt asynchronous dual-rail logic with dual-rail balanced logic and new dual-rail spacer latch. Common and Machine learning (ML) SCA simulations are performed to validate SCA resistance. To the best of our knowledge, we are the first ones to perform the ML SCA evaluations on asynchronous AES. Simulation results with 200K power traces demonstrate that our asynchronous AES is immune to the attacks. Our proposed asynchronous AES occupies an area of 0.016mm² in TSMC 28nm technology and consumes 1nJ per encryption at a supply voltage of 0.9V.

A miniaturized dual-band frequency selective surface (FSS) is proposed in this letter. The FSS unit cell is composed of meander lines arranged spirally, and produces resonant frequencies of 1.42GHz and 3.76GHz with -3dB bandwidths of 0.95GHz and 0.49GHz. The equivalent circuit model is introduced to explain the FSS performance. The meander lines at top and bottom layers are connected through copper vias to increase the equivalent inductance and capacitance of the FSS unit cell. The dimension of the unit cell is 10 mm, which is about 4.7% of the wavelength at the first resonant frequency. Simulation results show that the proposed FSS can work stably at resonant frequencies for both TE and TM polarizations while the incidence angle varies from 0 to 60 degree. A prototype of the FSS is fabricated and measured. The measurement results show reasonable agreement with the simulated results.

This paper reports slow-wave substrate integrated waveguide (SW-SIW) with rotary tensor unit cells and its applications to filters design. The proposed cross-shaped tensor unit cell can show anisotropic guided-wave parameters of interest, namely its equivalent permittivity and permeability along the transverse direction are different from those along the longitudinal direction. Hence, as rotating the tensor unit cells, equivalent permittivity and permeability of the SW-SIW will be varied, thus its guided-wave properties can be adjusted flexibly. Moreover, the proposed SW-SIW is utilized to constitute slow-wave cavity for filters design. By rotating the tensor unit cells with various angles, equivalent permeability and permittivity of the cavity can be changed as well, which will further influence the cavity’s resonant frequency differently. Experimental results of the proposed SW-SIW cavity filters are in good agreement with simulations, which indicate that the filters’ resonance and coupling properties can be adjusted by rotating the tensor unit cells.

It is necessary to solve the square root of the LC matrix when calculating the characteristic impedance matrix of multi-conductor transmission lines. This letter presents an algorithm based on the simple iteration method. There are no strict requirements for selecting initial values, which means that any initial value can converge to the correct solution. Based on this algorithm, a program is developed, and the solution is in agreement with other algorithm results.

Solenoid valves (SVs) as a kernel component are widely used in various control systems. Through accurately predicting the remaining useful life (RUL) of the SV, predictable maintenance its can be implemented to reduce system maintenance costs and system reliability improves. This paper proposes a frequency modulated continuous wave (FMCW) based on millimeter-wave radar and the auxiliary particle filter (APF) technique to estimate the RUL of SVs. Firstly, a 77GHz FMCW millimeter-wave radar with a single input and multiple outputs (SIMO) is used to obtain the core displacements of two SVs with the same frequencies. A degradation experiment is designed, and the distortion degree of the core displacement is taken as the degradation indicator to construct a degradation data set. Secondly, the APF technique is used to estimate the degradation state and RUL of the SV. Finally, an experiment platform is built using TI’s millimeter-wave radar to verify the method proposed in this paper. The experimental results show that the RUL estimation results are satisfactory.

This paper presents a phase-locking-loop-based (PLL-based) charge control scheme to enhance the cross regulation (CR) performance of charge-controlled SIMO Buck DC-DC without freewheel period. By combining PLL structure with the traditional charge control scheme, each channel could be regulated by an independent charge control loop. Moreover, a gain-adapted charge pump (GACP) technique is applied for the stability in multi-load condition. The multi-loop stability and CR expressions are derivated to improve their relative performance. Experimental results show that the proposed scheme can achieve worst-case CR of 0.052mV/mA in 384mA load transient, and 0.038mV/mA CR in 150mA load transient with at least 43.2% improvement above the existing charge control schemes.

Ring oscillators based physical unclonable functions (RO PUF) is a classical FPGA-friendly Weak PUF structure with better performance, but it can only produce limited challenge-response pairs (CRPs) with lack reliability. This paper proposes a new Strong RO PUF structure with highly reliability and enhanced challenge response pairs resilient to modeling attacks. It divides 2N RO rings into two groups and compares their cumulative frequency under the control of the N-bit challenge to generate 2^N CRPs. The reliability of each bit PUF responses is tested and marked in real time, and a highly reliable anti-fuse PUF structure is introduced to fuzzify the CRPs. FPGA verification results show that this bit self-test RO PUF (BST-RPUF) has a uniformity of 46.78% and a uniqueness of 48.64%, and the bit error rate of the marked reliable responses can be less than 10^-9.