A 14-Bit 2.8GS/s DAC with DTIRZ technique in 65 nm CMOS

Abstract

For high-speed current-steering digital-to-analog converters (DACs), the code-dependent inter-symbol-interference (ISI) is one of the most important factors affecting the dynamic performance. In this paper, a dual time-interleaved return-to-zero (DTIRZ) technique is proposed to suppress the code-dependent ISI without tightening the settling time and losing the output energy a lot in high-speed DACs. Two time-interleaved return-to-zero (RZ) codes are generated as a substitute for the traditional single non-return-to-zero (NRZ) code to control the quad-switching in DTIRZ. With the DTIRZ technique and a 4-channel parallel architecture, a 14-bit 2.8GS/s current-steering DAC is implemented in 65nm CMOS process. A specially-designed 4:2 MUX is adopted to generate the two time-interleaved RZ codes. The implemented DAC achieves > 50 dB SFDR for signals over the 1GHz bandwidth at 2.8 GS/s. It consumes a total power of 220 mW from a 1.2 V and a 3.3V supply.