IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 18 , Issue 6
Showing 1-8 articles out of 8 articles from the selected issue
LETTER
  • Yinghong Hu, Yuan Zhao, Yirun Ji, Tongxin Chen
    Type: LETTER
    Subject area: Power devices and circuits
    2021 Volume 18 Issue 6 Pages 20200440
    Published: March 25, 2021
    Released: March 25, 2021
    [Advance publication] Released: February 22, 2021
    JOURNALS FREE ACCESS

    In this paper, a novel zero-voltage and zero-current switching (ZVZCS) phase-shifted full-bridge (PSFB) converter is proposed to improve the efficiency of traditional PSFB converter. The proposed converter consists of two half-bridge inverters in the primary side and two center-tap rectifiers with one shared output filter in the secondary side. This structure allows the proposed converter to achieve a wide range of ZCS for lagging-leg switches and ZVS for leading-leg switches. The primary energy can be continuously transferred to the secondary side, which is helpful to reduce output filter requirement. The operational principle and design considerations are explained and analyzed in detail. A laboratory prototype with 320-385-V input 50-V/20-A output is built to verify the superior features of the proposed converter.

    Download PDF (599K)
  • Yang Li, Chao Fu, Tao Jiang, Yang Liu, Cheng Ma, Jan Bogaerts, Xinyang ...
    Type: LETTER
    Subject area: Integrated circuits
    2021 Volume 18 Issue 6 Pages 20210021
    Published: March 25, 2021
    Released: March 25, 2021
    [Advance publication] Released: March 03, 2021
    JOURNALS FREE ACCESS

    In this paper, we present a pixel array operation method of CMOS image sensor that enables pipeline processing of pixel operations. The sensor frame rate constraint from the delay of pixel array control lines is much relieved by manipulating control phases of adjacent pixel rows simultaneously. An analog frontend readout circuit is proposed to support the row pipeline operation pixel readout. A prototype image sensor was designed with its performance characterized and analyzed.

    Download PDF (875K)
  • Minshin Cho, Jae Young Hur, Wooyoung Jang
    Type: LETTER
    Subject area: Integrated circuits
    2021 Volume 18 Issue 6 Pages 20210027
    Published: March 25, 2021
    Released: March 25, 2021
    [Advance publication] Released: February 09, 2021
    JOURNALS FREE ACCESS

    In this letter, we propose a novel prefetching technique that is free from cache pollution and thus achieves high performance for multicore processors. Unlike the conventional prefetchers that cause incorrect predictions, the proposed prefetcher reads instructions in advance only in determined paths and charges dynamic random access memory (DRAM) cells storing instructions in undetermined paths via refreshing DRAM cells. The DRAM cells highly charged will be quickly accessed. Since caches served by our prefetcher always store useful instructions, as a result, they are free from cache pollution that results in lower cache hit rate. In the case that SPEC CPU2006 benchmarks run on an 8-core processor, the proposed prefetcher consumes more 3.2% DRAM power, but achieves 12% higher performance on average.

    Download PDF (535K)
  • Xiaobo Su, Zongguang Yu, Yingdan Jiang, Zihao Jiao, Lin Zhao, Zhenhai ...
    Type: LETTER
    Subject area: Integrated circuits
    2021 Volume 18 Issue 6 Pages 20210043
    Published: March 25, 2021
    Released: March 25, 2021
    [Advance publication] Released: February 22, 2021
    JOURNALS FREE ACCESS

    For high-speed current-steering digital-to-analog converters (DACs), the code-dependent inter-symbol-interference (ISI) is one of the most important factors affecting the dynamic performance. In this paper, a dual time-interleaved return-to-zero (DTIRZ) technique is proposed to suppress the code-dependent ISI without tightening the settling time and losing the output energy a lot in high-speed DACs. Two time-interleaved return-to-zero (RZ) codes are generated as a substitute for the traditional single non-return-to-zero (NRZ) code to control the quad-switching in DTIRZ. With the DTIRZ technique and a 4-channel parallel architecture, a 14-bit 2.8GS/s current-steering DAC is implemented in 65nm CMOS process. A specially-designed 4:2 MUX is adopted to generate the two time-interleaved RZ codes. The implemented DAC achieves > 50 dB SFDR for signals over the 1GHz bandwidth at 2.8 GS/s. It consumes a total power of 220 mW from a 1.2 V and a 3.3V supply.

    Download PDF (1376K)
  • Xiaojian Zhu, Runxi Zhang, Chunqi Shi
    Type: LETTER
    Subject area: Integrated circuits
    2021 Volume 18 Issue 6 Pages 20210049
    Published: March 25, 2021
    Released: March 25, 2021
    [Advance publication] Released: February 26, 2021
    JOURNALS FREE ACCESS

    This paper presents a high gain millimeter-wave (mmW) power amplifier (PA) fabricated in a 55nm CMOS technology for V-band 5G wireless communication applications. An accurate magnetically-coupled-resonator (MCR) analysis and evaluation method is proposed to capture the MCR characteristics and optimize PA gain and bandwidth. A low-loss-matching-resonator (LLMR) technology is developed to enhance power gain and efficiency. The PA achieves a peak gain of 21.1dB at 67GHz with a 3dB bandwidth (BW-3dB) of 10GHz. At 67GHz, the measured saturated output power (Psat), the output 1dB compression point (OP1dB) and the peak PAE are 13.9dBm, 9.7dBm and 11.8%, respectively.

    Download PDF (3007K)
  • Junichiro Nagao, Urmimala Chatterjee, Xiangdong Li, Jun Furuta, Stefaa ...
    Type: LETTER
    Subject area: Power devices and circuits
    2021 Volume 18 Issue 6 Pages 20210059
    Published: March 25, 2021
    Released: March 25, 2021
    [Advance publication] Released: March 01, 2021
    JOURNALS FREE ACCESS

    A three-level gate driver and a power Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) were monolithically integrated to prevent false turn-on, reduce reverse conduction loss and realize fast switching. The proposed gate driver works with an external and an integrated capacitor which supply negative gate voltage. Monolithic integration makes power conversion circuits smaller in size and improves circuit performance due to its lower parasitics. The integrated MIM (Metal-Insulator-Metal) capacitor improves dv/dt immunity. Measurement results showed that the proposed GaN-IC realized fast switching speed of 3.7ns ton and 6.1ns toff, and improved efficiency of an SR buck-converter.

    Download PDF (1135K)
  • Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru ...
    Type: LETTER
    Subject area: Integrated circuits
    2021 Volume 18 Issue 6 Pages 20210065
    Published: March 25, 2021
    Released: March 25, 2021
    [Advance publication] Released: March 08, 2021
    JOURNALS FREE ACCESS

    This paper proposes a ring oscillator (ROSC) for extremely low-voltage LSI applications. The ROSC consists of dedicated low-voltage stacked body bias inverters (SBBIs) that are based on the conventional self-bias inverter (SBI) and stacked inverter (SI). The proposed SBBI employs the advantages of both SBI and SI to oscillate at extremely low supply voltage. The voltage gain of the proposed SBBI is improved by controlling main inverter’s supply (VDD and Gnd) and body-bias voltages, by using stacked and feedback inverters. The novelty of our proposed SBBI is in the combination of the conventional low-voltage circuit design techniques and its demonstration at extremely low supply voltage. Simulated and measured results in a 0.18-µm CMOS process with deep n-well option demonstrated that the proposed ROSC can operate at extremely low supply voltage of 35 mV and generate a clock with an 88% voltage swing from an input supply voltage of 50 mV. To the best of the authors’ knowledge, this is the lowest supply voltage CMOS ring oscillator ever reported.

    Download PDF (3475K)
  • Shouyang Zhai, Xiang Zhou, Peng Hu, Yan Chen, Dan Chen, Zhongyuan Zhou ...
    Type: LETTER
    Subject area: Electromagnetic theory
    2021 Volume 18 Issue 6 Pages 20210069
    Published: March 25, 2021
    Released: March 25, 2021
    [Advance publication] Released: March 03, 2021
    JOURNALS FREE ACCESS

    For arbitrary electrically large cavities, the ideal reverberant frequency is of critical to predict the response of the reference antenna or the electronics inside. To determine the ideal reverberant frequency, this work has carried out a comparison study on the scattering parameter S11 and S21 based methods for the general case in reverberation chamber (RC). For the two methods, both of them share the same theoretical basis according to the ergodicity principle, i.e., the ideal field distribution and the commonly used correlation analysis. While for arbitrary electrically large cavities, the S11 samples rely on the mechanical stirrer (which is not easy to be equipped like that of a classic RC), S21 samples are more easily recorded by frequency stirring technique. And the corresponding experimental results show that the S21 based method can provide a more conservative estimate of the ideal reverberant frequency.

    Download PDF (4227K)
feedback
Top