Low jitter design for quarter-rate CDR of 100Gb/s PAM4 optical receiver

Abstract

In the ultra-high speed four-level pulse amplitude modulation (PAM4) optical receiver, the data phase jitter is deteriorated by inter-symbol interference (ISI), level transitions and sampling clock. This paper analyzed in detail the causes of phase jitter, and then proposed a novel PAM4 clock and data recovery (CDR) architecture. A three-lane quarter-rate phase detector with majority voter was employed to suppress the input phase jitter caused by discrete zero-crossings, and an optimized quadrature voltage-controlled oscillator (QVCO) was designed to provide stable and precise sampling clock. The PAM4 CDR was optimally designed based on IHP 0.13µm SiGe BiCMOS process, and the post-simulation results indicates that our CDR can operate properly at 100Gb/s with a peak-to-peak jitter of 5.52ps.