Unit cell mismatch scrambling method for high-resolution unary DAC based on virtual 3D layout

Dan Yao; Xuanyan Bai; Shogo Katayama; Anna Kuwana; Kazuyuki Kawauchi; Haruo Kobayashi; Kouji Hirai; Akira Suzuki; Satoshi Yamada; Tomoyuki Kato; Ritsuko Kitakoga; Takeshi Shimamura; Gopal Adhikari; Nobuto Ono; Kazuhiro Miura; Shigeya Yamaguchi

doi:10.1587/elex.19.20220430

LETTER

Unit cell mismatch scrambling method for high-resolution unary DAC based on virtual 3D layout

Dan Yao, Xuanyan Bai, Shogo Katayama, Anna Kuwana, Kazuyuki Kawauchi, Haruo Kobayashi, Kouji Hirai, Akira Suzuki, Satoshi Yamada, Tomoyuki Kato, Ritsuko Kitakoga, Takeshi Shimamura, Gopal Adhikari, Nobuto Ono, Kazuhiro Miura, Shigeya Yamaguchi

Author information

Dan Yao
Division of Electronics and Informatics, Gunma University
Xuanyan Bai
Division of Electronics and Informatics, Gunma University
Shogo Katayama
Division of Electronics and Informatics, Gunma University
Anna Kuwana
Division of Electronics and Informatics, Gunma University
Kazuyuki Kawauchi
Division of Electronics and Informatics, Gunma University
Haruo Kobayashi
Division of Electronics and Informatics, Gunma University
Kouji Hirai
Jedat Inc.
Akira Suzuki
Jedat Inc.
Satoshi Yamada
Jedat Inc.
Tomoyuki Kato
Jedat Inc.
Ritsuko Kitakoga
Jedat Inc.
Takeshi Shimamura
Jedat Inc.
Gopal Adhikari
Jedat Inc.
Nobuto Ono
Jedat Inc.
Kazuhiro Miura
Jedat Inc.
Shigeya Yamaguchi
Jedat Inc.

Keywords: unary DAC, mismatch scrambling, dynamic element matching, virtual 3D layout of unit cells, SFDR

JOURNAL FREE ACCESS

2022 Volume 19 Issue 24 Pages 20220430

DOI https://doi.org/10.1587/elex.19.20220430

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Abstract

The paper studies a unit cell mismatch scrambling method for a high-resolution unary DAC based on virtual 3-dimensional (3D) layout, to improve its spurious-free dynamic range (SFDR) for communication applications. This can be implemented with relatively simple interconnections and scrambling circuits, compared to that based on the 2-dimentional (2D) layout.

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