Two novel PSRR enhancement techniques for voltage reference of depletion NMOS

抄録

Two novel PSRR characteristic enhancement technologies based on the voltage reference (VR) is presented: Double-reference PSRR stacking technology (DRPST) and Pre-regulated-current technology (PRCT). The above two novel technologies are explained by designing two voltage reference structures. The voltage reference is obtained by a depletion NMOS and an enhancement NMOS. Structure I employs DRPST compared with the traditional Pre-regulated-voltage technology (PRVT) to improve the PSRR. Structure II uses PRCT composed of DRPST and improved Pre-regulated-voltage technology (IPRVT) to improve PSRR. The above two structural reference sources are simulated in standard 0.18µm CMOS process. When the output reference is 810mV, the PSRR of VR obtained in Structure I is -140dB@1KHz at TT corner with the line sensitivity: LS =0.023%/V, the temperature coefficients: TC=4.2ppm/^°C; The PSRR of the Structure II is -114dB@1KHz at TT corner with LS =0.013%/V, TC =7.5ppm/^°C.