FPGA-based high-throughput Montgomery modular multipliers for RSA cryptosystems

抄録

This paper presents an FPGA-based Montgomery modular multiplier for implementing high-throughput RSA cryptosystems. First, we propose a variable segmentation Montgomery modular multiplication (VSMMM) algorithm which enables the radix of the multiplier and the multiplicand adapt to any given datawidth. Then, to make trade-offs among latency, area and throughput, we design a dual-path fully concurrent MMM architecture based on VSMMM algorithm. As a case study, a RSA processor has been implemented using the proposed method. Experimental results show that the proposed MMM multiplier and RSA processor achieve much higher throughput than existing works.