IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter
Tomohiko ItoTakeshi UenoDaisuke KuroseTakafumi YamajiTetsuro Itakura
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2005 Volume 2 Issue 15 Pages 429-433

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Abstract

The optimum bit/stage configuration is an important issue in the design of a low-power pipeline analog-to-digital converter (ADC). Prior to this work, power considerations based on a linear-model have been reported [1]. In this letter, the slew-rate limitation, a non-linear effect, is taken into consideration in low-power design. In the case of a 10-bit, 200-MSPS ADC using 90-nm CMOS technology, the lowest power bit-arrangement was found to be 1.5bit/stage. A test chip was fabricated for confirmation, and a power dissipation of 105mW was achieved.

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© 2005 by The Institute of Electronics, Information and Communication Engineers
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