The optimum bit/stage configuration is an important issue in the design of a low-power pipeline analog-to-digital converter (ADC). Prior to this work, power considerations based on a linear-model have been reported . In this letter, the slew-rate limitation, a non-linear effect, is taken into consideration in low-power design. In the case of a 10-bit, 200-MSPS ADC using 90-nm CMOS technology, the lowest power bit-arrangement was found to be 1.5bit/stage. A test chip was fabricated for confirmation, and a power dissipation of 105mW was achieved.
We present evaluation results for DC offset in the direct conversion receiver for W-CDMA with low current consumption. Measured results indicate that steady-state DC offset is suppressed to less than 30mV and transitional variation in DC offset with gain change is limited to around 100mV. The computer simulation revealed that negligible degradation in bit error rate (BER) performance due to the DC offset transition occurs with the proposed receiver.