IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Using simulated annealing to generate input pairs to measure the maximum power dissipation in combinational CMOS circuits
Alberto Palacios Pawlovsky
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2005 Volume 2 Issue 4 Pages 115-120


With the advent of chips that nearly hold 2 billion transistors, low power design is extremely important. We need tools that let us measure the power dissipation of our circuits to choose the lowest power design. For this, we need to generate the inputs that cause the maximum power dissipation in each one of our design choices. In this work we show the results we obtained applying the simulated annealing algorithm in the generation of these input patterns for the ISCAS85 combinational circuits. In our experiments we got for most of the circuits better results than those previously reported elsewhere.

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© 2005 by The Institute of Electronics, Information and Communication Engineers
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