IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 2 , Issue 4
Showing 1-5 articles out of 5 articles from the selected issue
LETTER
  • A. Torralba, R. G. Carvajal, M. Jiménez, F. Muñoz, J. Ra ...
    2005 Volume 2 Issue 4 Pages 103-107
    Published: 2005
    Released: February 25, 2005
    JOURNALS FREE ACCESS
    Class-AB circuits, which are able to deal with currents which are orders of magnitude larger than their quiescent current, are good candidates for low-power analog design. This paper presents a new, simple, class-AB current-mirror, based on the Flipped Voltage Follower [1]. In the authors knowledge this is the first class-AB current-mirror which operates with a supply voltage smaller than two transistor threshold voltages without an additional clock signal or voltage doubler. Experimental results are provided which show proper operation at 1.5V in a 0.5µm standard CMOS technology.
    Download PDF (736K)
  • Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng
    2005 Volume 2 Issue 4 Pages 108-114
    Published: 2005
    Released: February 25, 2005
    JOURNALS FREE ACCESS
    The three-dimension scheduling is defined as the simultaneous application of clock selection and operation scheduling. Previous three-dimension scheduling approach does not consider the interconnect delay. However, with the advent of nanometer era, the interconnect delay may take multiple clock cycles. In this paper, we use convex programming to formulate the three-dimension scheduling problem under multi-cycle interconnect communications. Benchmark data consistently show that our approach achieves the minimum latency within an acceptable run time.
    Download PDF (360K)
  • Alberto Palacios Pawlovsky
    2005 Volume 2 Issue 4 Pages 115-120
    Published: 2005
    Released: February 25, 2005
    JOURNALS FREE ACCESS
    With the advent of chips that nearly hold 2 billion transistors, low power design is extremely important. We need tools that let us measure the power dissipation of our circuits to choose the lowest power design. For this, we need to generate the inputs that cause the maximum power dissipation in each one of our design choices. In this work we show the results we obtained applying the simulated annealing algorithm in the generation of these input patterns for the ISCAS85 combinational circuits. In our experiments we got for most of the circuits better results than those previously reported elsewhere.
    Download PDF (420K)
  • Hideaki Okayama
    2005 Volume 2 Issue 4 Pages 121-126
    Published: 2005
    Released: February 25, 2005
    JOURNALS FREE ACCESS
    A simple integrated deflector and grating structure is proposed for a wavelength filtering. The deflector is composed of a channel waveguide and a slab waveguide with a tapered gap between them to generate a Gaussian light beam in the slab waveguide. The echelle type grating is formed at the end of the slab waveguide. The distance between the grating and the deflector is 100-200µm. The device is designed using diffraction theory. The filter response is verified using bi-directional BPM. Tuning range of 25nm for 5.4 × 10-3 refractive index change and filter passband width of 15nm were attained by a 350µm long device at 1500nm wavelength.
    Download PDF (303K)
  • J. Ramírez-Angulo, Milind S. Sawant, A. J. López-Mart&ia ...
    2005 Volume 2 Issue 4 Pages 127-132
    Published: 2005
    Released: February 25, 2005
    JOURNALS FREE ACCESS
    A low distortion low-voltage BiCMOS OTA with wide gm adjustment range and constant input range is presented. It is based on a highly linear voltage-to-current converter input stage merged with translinear loops that implement linear electronically programmable current mirrors. Experimental results are provided that confirm the characteristics of the proposed OTA with a single 1.7V supply, 1.2V input range, two decades gain adjustment range, and 0.3% THD.
    Download PDF (352K)
feedback
Top