High-speed and low-power embedded TEC BCH scheme for ReRAM array

Abstract

This paper proposes an embedded TEC BCH scheme for ReRAM array, which is capable of low access time and uniform error distribution. The high speed decoder with SBSA is proposed with a fully-parallel architecture. An optimized adaptive error correction approach is utilized to reduce the power consumption. Furthermore, the composite field arithmetic is used to minimize the logical size. For the performance evaluation, the decoder is implemented on a Xilinx Virtex-7 FPGA, and synthesized with 65nm CMOS technology, which can achieve a 62.72Gb/s throughput at a decoding frequency of 490MHz and 0.95ns decoding delay with a 774.1μW power consumption.