A virtual zero power (VZP) method was used to reduce the power consumption of hybrid magnetic bearings (HMBs) in left ventricular assist devices (LVADs). The mathematics of the HMB system in LVAD was established, and the stability was analyzed with a proportional-derivative (PD) controller. The unbalanced forces on the rotor can be identified by the output voltage of the PD controller, together with the negative stiffness of the permanent magnet, and the rotor can be suspended at a point where the rotor’s reluctant force is at a minimum to lower power consumption. Experiments were conducted to measure the power consumption of the magnetic bearing at different rotational speeds, and different trajectories of the rotor were demonstrated. The results showed HMB using VZP consumed 0.28W averagely at 1000-4000rpm in the LVAD.
This paper proposes an embedded TEC BCH scheme for ReRAM array, which is capable of low access time and uniform error distribution. The high speed decoder with SBSA is proposed with a fully-parallel architecture. An optimized adaptive error correction approach is utilized to reduce the power consumption. Furthermore, the composite field arithmetic is used to minimize the logical size. For the performance evaluation, the decoder is implemented on a Xilinx Virtex-7 FPGA, and synthesized with 65nm CMOS technology, which can achieve a 62.72Gb/s throughput at a decoding frequency of 490MHz and 0.95ns decoding delay with a 774.1μW power consumption.
Based on the self-developed standard process RF-LDMOS device, a new ultra-wideband RF power amplifier is designed in this letter. The amplifier removes the absorbing resistor and capacitor series structure at the end of the drain. The stability of the circuit is enhanced by the pre-matching circuit. Considering the small impedance value of the RF high-power device, it is difficult to achieve broadband matching. The novel tapering drain transmission has been developed which overcomes the distributed amplifier’s limitations of low power and efficiency. Ultra-wideband RF amplifier has excellent output power and efficiency. The measurement results show that from 0.8-2.2GHz, under the condition of 28V power supply, the saturated output power is 43dBm (20W), the power gain is 10dB, the drain efficiency is about 30%-50%; The peak-to-average ratio is 8dB, and the ACPR is less than -41dBc when the linear output is 5W, proving the effectiveness of the new tapered drain structure to achieve broadband.
This paper presents a fully integrated Ku-band transmitter front-end with high image rejection ratio (IRR), local oscillator feedthrough (LOFT) suppression, gain and output power for point-to-point (P2P) communication. To avoid the bulky off-chip image-rejection filter, the Hartley transmitter structure is employed, in which frequency plan is undertaken to improve the IRR and LOFT performance, and a two-stage polyphase filter (PPF) and an in/quadrature-phase (I/Q) Gilbert mixer are utilized to improve the IRR further. With the capacitive neutralization and transformer-based series power combining techniques, a two-stage power amplifier (PA) is used to obtain high gain and output power. In the LO buffer, a flexible phase inverting cascode structure is used to achieve reliable up-sideband operation, and the inductive peaking technique and cross-coupled transistor pair are employed to promote the LO swing. Fabricated in a 65-nm CMOS process, the proposed Ku-band transmitter occupies a chip area of 0.98mm2, and consumes 304-mW power consumption from a 1.2-V supply voltage. With measurements, over 15.8-17.9-GHz radio frequency (RF) bandwidth, the transmitter achieves an IRR and LOFT suppression ratio of 45-55 and 43-52dBc, respectively. Moreover, it exhibits a conversion gain of 28.5dB, an output 1-dB compression point (OP1dB) of 13.3dBm and a saturated output power (Psat) of 16dBm.
We propose a novel approach for real-time generation of random walk noise. Our approach aims to generate natural laser phase noise and construct a linewidth tunable laser. By utilizing field- programmable gate array circuits and digital-to-analog converters, we generate noise that is subsequently combined with low-frequency analog noise. This combined noise is then fed into a lithium niobate phase modulator to emulate phase fluctuations. Our method facilitates accurate control over the laser linewidth spectrum, closely approximating actual noise characteristics.
A novel constant-gm rail-to-rail input stage for CMOS operational amplifier is presented in this paper. The input stage mainly consists of a PMOS transistors differential pair and a NMOS transistors differential pair placed in parallel as a rail-to-rail differential input stage and the tail currents of the two differential pairs are controlled by a PMOS and a NMOS common-mode voltage sensor respectively. The gm of the input stage of the operational amplifier could be a constant value within the input common-mode voltage. The simulation result shows that when the power supply voltage is 1.8V and 3.3V respectively, the gm variation in the entire input range (0∼1.8V or 0∼3.3V) is within ±1.38% and ±3.38%. The power dissipation is 36.9μW and 51.74μW. SMIC 55nm CMOS process and Cadence SPECTRE simulator are used to layout and simulate this work.
The quasi-newton methods are one of the most effective methods for solving unconstrained optimization problems. This letter provides a hardware-efficient massive multiple-input multiple-output (MIMO) detector using an improved quasi-newton (IQN) method. Due to the similarity in the stepsize calculation of Barzilai-Borwein and limited-memory BFGS, two quasi-newton methods are deeply fused in the proposed IQN algorithm for higher convergence speed. The corresponding efficient detector architecture is also given, in which a dual-track systolic array architecture is employed to diminish the number of required Processing Elements (PE) by nearly half with less computational delay. Furthermore, an approximate divider based on the Goldschmidt method is designed to further reduce hardware overhead. Simulation results show that the proposed IQN algorithm achieves better Bit-Error-Ratio (BER) performance under different antenna configurations, and FPGA implementation results also validate the superiority of the proposed detector in terms of hardware efficiency over the state-of-the-art (SOTA) detectors.