A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM

抄録

A capacitor-coupled stacked-based sense amplifier (CC-STSA) is proposed to compensate the input-referred offset voltage (V_OS), which dictates the minimum required bitline swing for a reliable read operation of static random access memory (SRAM). The data-aware coupled capacitors are employed to dynamically tune the driving ability of sensing transistors according to the data supposed to be read, thus improving the offset tolerance of sense amplifier (SA). Compared with the conventional current latch-type SA (CLSA), the simulation results in 55-nm CMOS technology show that the proposed scheme achieves more than 4.17X of the standard deviation of V_OS (σ_OS) reduction across the range of supply voltage from 0.6V to 1.2V and reduce the read energy consumption and read delay to 54.9% and 45.5% respectively. Furthermore, the proposed scheme reduces the σ_OS by 2.19X compared to DIBBSA on average.