Structural analysis attack on asynchronous obfuscated circuits

Abstract

Logic locking is an efficient circuit encryption method aimed at protecting the intellectual properties (IPs) of hardware designs. It can provide protection against various hardware security threats throughout the IC manufacturing supply chain. Recently, a timing-based logic locking approach known as Data Flow Obfuscation (DFO) has been proposed. DFO creates key-based data flow within the locked circuit, offering resistance against combinational SAT attacks, sequential SAT attacks, CycSAT, and Removal Attacks concurrently. In this paper, we present an approach to unlocking Data flow Obfuscation that is based on structure analysis and SAT solver. Specifically, we first identify the characteristics of obfuscated circuits on signal transition graph and asynchronous pipeline, then conduct structural analysis to prune the key, apply SAT attacks to divide the circuit into real paths and false paths, and finally recover the key. We evaluate on ISCAS’89/ITC’99 locked benchmarks and are able to recover keys in all cases.