IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Current issue
Displaying 1-7 of 7 articles from this issue
LETTER
  • Xiuping Wang, Chuqiao Zhou, Chunyu Qu, Jiawei Zhang, Dong Xu
    Article type: LETTER
    Subject area: Power devices and circuits
    2024 Volume 21 Issue 11 Pages 20230596
    Published: June 10, 2024
    Released on J-STAGE: June 10, 2024
    Advance online publication: March 21, 2024
    JOURNAL FREE ACCESS

    To make the motor perform better during operation, a conical outer rotor structure is proposed based on the traditional outer rotor permanent magnet vernier motor (PMVM) structure. The electromagnetic characteristics of PMVM and COR-PMVM are compared and analyzed. The parameters of COR-PMVM are optimized, and the motor’s temperature rise is simulated and analyzed by magneto-thermal coupling. Simulation results demonstrate a 39.3% increase in electromagnetic torque of the engine, and a 33.3% reduction in torque ripple. The stator and winding can reach a temperature of 101.72°C, whereas the rotor and permanent magnet remain cooler at 70°C. Lastly, a temperature rise experiment is conducted on the permanent magnet motor to validate the precision of the magneto-thermal coupling analysis method.

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  • Peixuan Jiang, Bo Gao, Yuheng Gao, Jialu Wang, Xiao Wang, Ping Wang, X ...
    Article type: LETTER
    Subject area: Power devices and circuits
    2024 Volume 21 Issue 11 Pages 20240058
    Published: June 10, 2024
    Released on J-STAGE: June 10, 2024
    Advance online publication: March 28, 2024
    JOURNAL FREE ACCESS

    Hybrid switch (HyS) consisting of Si IGBT and SiC MOSFET becomes increasingly popular due to its prominent advantages of low power loss and cost in clear energy era. However, the existing studies suffer from the current measurement methods due to the insertion inductance and inductive signal overshoot, which may lead to inaccurate measurements of loss, electrical stress and also limited performance of HyS at high switching frequencies. This paper conducts an in-depth study on the impact of inner loop inductance on HyS turn-off process. And an accurate current measurement method is proposed for high frequency HyS test and application, showing significant improvement in insertion inductance level and high-bandwidth accuracy.

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  • Seo U Yeol, Lee Jeong Min, Kwon Sang Wook, Yong Seo Koo
    Article type: LETTER
    Subject area: Electron devices, circuits and modules
    2024 Volume 21 Issue 11 Pages 20240097
    Published: June 10, 2024
    Released on J-STAGE: June 10, 2024
    Advance online publication: April 19, 2024
    JOURNAL FREE ACCESS

    Circuit systems operating in low-voltage applications must provide stable output despite changes in load current. And without IC-level reliability, stable output voltage cannot be guaranteed. In this paper, the LDO regulator is designed to supply and discharge current in a switch format according to changes in load current. Additionally, an ESD protection circuit is absolutely required at the IC level. Therefore, in this paper, area efficiency and high robustness characteristics were verified by developing the ESD protection circuit, rather than using the conventional diode method to prevent ESD phenomenon. As a result, the proposed LDO regulator implemented in the 0.13µm BCD process was confirmed to maintain an undershoot voltage of 87.1mV and an overshoot voltage of 94.1mV at a load current of 350mA.

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  • Zihe Wang, Dongliang Xiong, Kai Huang
    Article type: LETTER
    Subject area: Integrated circuits
    2024 Volume 21 Issue 11 Pages 20240107
    Published: June 10, 2024
    Released on J-STAGE: June 10, 2024
    Advance online publication: April 25, 2024
    JOURNAL FREE ACCESS

    Logic locking is an efficient circuit encryption method aimed at protecting the intellectual properties (IPs) of hardware designs. It can provide protection against various hardware security threats throughout the IC manufacturing supply chain. Recently, a timing-based logic locking approach known as Data Flow Obfuscation (DFO) has been proposed. DFO creates key-based data flow within the locked circuit, offering resistance against combinational SAT attacks, sequential SAT attacks, CycSAT, and Removal Attacks concurrently. In this paper, we present an approach to unlocking Data flow Obfuscation that is based on structure analysis and SAT solver. Specifically, we first identify the characteristics of obfuscated circuits on signal transition graph and asynchronous pipeline, then conduct structural analysis to prune the key, apply SAT attacks to divide the circuit into real paths and false paths, and finally recover the key. We evaluate on ISCAS’89/ITC’99 locked benchmarks and are able to recover keys in all cases.

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  • Huu-Thuan Huynh, Tan-Phat Dang, Tuan-Kiet Tran, Trong-Thuc Hoang, Cong ...
    Article type: LETTER
    Subject area: Devices, circuits and hardware for IoT and biomedical applications
    2024 Volume 21 Issue 11 Pages 20240156
    Published: June 10, 2024
    Released on J-STAGE: June 10, 2024
    Advance online publication: April 30, 2024
    JOURNAL FREE ACCESS

    Nowadays, almost all fields cannot lack security, from the essential encryption/decryption to hash function algorithms. The Secure Hash Algorithm 3 (SHA-3) with four modes, SHA3-224/256/384/512, is a known new hash function due to being more secure than its predecessors, SHA-1 and SHA-2. While hardware implementations of SHA-3 have been extensively studied, the primary focus has often been on optimizing the KECCAK algorithm. This paper introduces an efficient multimode SHA-3 architecture (MS3) featuring configurable buffers and a sub-pipeline KECCAK design. These innovations aim to save resources and boost throughput, respectively. Furthermore, MS3 is integrated with the reduced instruction set computer five (RISC-V) system as a hardware accelerator via the TileLink bus. This integration enables MS3 to communicate with RISC-V for configuration purposes and utilize direct memory access (DMA) for efficient data transfer with memory. Experimental results on the Cyclone IV E platform demonstrate MS3 achieving approximately 500Mbps throughput across all modes, with DMA achieving a throughput of 540.21Mbps. Additionally, our design exhibits superior efficiency compared to existing works on Virtex 5, 6, and 7 FPGA platforms. Specifically, MS3 achieves throughputs of 11.07Gbps, 14.52Gbps, and 17.29Gbps, with corresponding efficiencies of 10.31Mbps/Slice, 15.03Mbps/Slice, and 18.39Mbps/Slice, respectively.

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  • Rui Hu, Linhong Lu, Zhongchen Bai, Fashun Yang, Kui Ma, Zhao Ding
    Article type: LETTER
    Subject area: Power devices and circuits
    2024 Volume 21 Issue 11 Pages 20240185
    Published: June 10, 2024
    Released on J-STAGE: June 10, 2024
    Advance online publication: April 17, 2024
    JOURNAL FREE ACCESS

    In the research on heat dissipation technology of power chips, the back thinning method is adopted. However, the back thinning technology is facing the risk of causing damage to the chips because the mechanical support capacity of the chip is significantly reduced. To improve the heat dissipation capacity of the back side of the power chips while not affecting the mechanical support, the back side grid type thermal TSV (GT-TTSV) heat dissipation structure is proposed. Based on the proposed heat transfer structure, the heat dissipation structure is optimized and verified, and compared with the heat dissipation structure of back thinning technology. Simulation comparative study shows that the proposed structure has better heat dissipation ability and thermal reliability.

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  • Ying He, Liang Chen, Xuanjin Sun
    Article type: LETTER
    Subject area: Power devices and circuits
    2024 Volume 21 Issue 11 Pages 20240211
    Published: June 10, 2024
    Released on J-STAGE: June 10, 2024
    Advance online publication: April 19, 2024
    JOURNAL FREE ACCESS

    This paper focuses on the Buck-Boost converter and presents a new approach to improve its efficiency and voltage transformation capability. The approach involves introducing a coupled inductor structure and restructuring the quadric front-end unit to ensure continuous input inductor current. The converter also uses a diode-capacitor (D-C) double-branch structure of switched capacitors to expand the output range and reduce voltage stress on each device. In addition, the converter utilizes the leakage inductance energy to suppress the current surge in the switched capacitor, achieving soft switching. The paper provides a detailed theoretical analysis and compares various indicators horizontally in different converters. Moreover, an experimental prototype of 200W was built to verify the design expectations and theoretical analysis through experiments.

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