A 10-bit 40MS/s SAR ADC with a low-noise low-offset dynamic comparator and a high-linearity sampling switch

抄録

This paper presents a 10-bit 40MS/s successive-approximation-register analog-to-digital converter (SAR ADC). To enhance the performance of the ADC, a high-linearity CMOS complementary bootstrap sampling switch (B-CMOS-SW) and a low-offset, low-noise double-tail dynamic comparator (LOLN-DT) are proposed. The ADC with the proposed comparator and the bootstrap switch is fabricated in a 40-nm 1P6M CMOS technology. Simulation results show that the proposed comparator achieves a low offset voltage of 3.4mV at 1σ, which reduces half compared with conventional Double tail (DT) dynamic comparator, and the input reference noise is 0.3mV at 1σ. Also, the proposed bootstrap switch improves the sampling nonlinearity above 6dB. At 1.2V supply and 40MS/s, the ADC reaches a SINAD of 57dB, the SFDR reaches more than 70dB, and the power consumption is 0.2mW, leading to a figure-of-merit (FOM) of 9.76fJ/conversion-step.