A 13dBm 25.7% PAE 25.3-dB gain E-band power amplifier in 40nm CMOS technology

抄録

An E-Band three-stage power amplifier (PA) in 40nm CMOS is presented in this paper. Since the significant difference in two sides’ impedance, the transformer for matching is difficult to achieve. To address that issue, a transform process is proposed for the transformer. The high peak power-added efficiency (PAE) design and the meticulous layout deployment are applied for a good performance. With a supply voltage of 1.1V, this PA achieves a power gain of 25.3dB with the 3-dB gain bandwidth of 11.2GHz (71.8-83GHz), a saturated output power of 13dBm, and a peak PAE of 25.7% at 76GHz with power dissipation of 79.2mW. The whole core size is only 0.52×0.14mm².