A 353pW, 0.014%/V line sensitivity self-biased CMOS voltage reference with source degeneration active load

Abstract

This paper proposes a self-biased sub-threshold CMOS voltage reference for ultra-low-power application. In the current generation path, a source degeneration active load (SDAL) is added to reduce the variation of the reference current (I_R) which helps to produce a stable voltage reference (V_REF). Moreover, by utilizing the line sensitivity (LS) improving circuit, the dependence of V_REF on the supply voltage (V_DD) can be largely reduced. The proposed design is fabricated in a standard 0.18-µm CMOS process. 11-chip measurement results show the prototype design can provide an 147.1mV average voltage with a minimum power consumption of 353pW at 27°C. The line sensitivity (LS) is only 0.014%/V, while the power supply rejection ratio (PSRR) at 10Hz is -68dB. The average temperature coefficient (TC) is 72ppm/°C from -20°C to +80°C, and the die area is only 0.0019mm².