Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an ‘error’ signal used to dynamically regulate the chip’s operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.

To improve the operational performance of Permanent Magnet Synchronous Motors (PMSM), a new voltage optimization algorithm is proposed. This algorithm is based on Particle Swarm Optimization (PSO) and incorporates two improvements: online optimization and secondary optimization. The improved PSO (IPSO) algorithm is applied to Dual-Vector Model Predictive Control (DVMPCC) for simulation and experimental research. The results show that, compared to DVMPCC, with similar speed response, the current ripple is reduced by 16.22% and the steady-state speed fluctuation is reduced by 65.14%. This indicates that the proposed algorithm is feasible and effectively improves the operational performance of the system.

Arbiter physically unclonable function (APUF) is one of the most representative strong PUFs. Improving traditional APUF can enhance the performance of APUF-based PUFs. Accordingly, based on the theoretical foundation of traditional APUF, this paper proposes a novel PUF that utilizes the threshold loss, in which the PMOS transmits at a low level and the NMOS transmits at a high level, as the deviation source. In this manner, we significantly extended the delay deviation of both the rising and falling edges, thereby improving the randomness of PUF. The proposed PUF passed six subtests of the NIST randomness test suite. The delay unit only uses 20 minimum-size transistors with a fully custom layout area of 6.14µm² in the TSMC 65-nm process, reducing the area by 15% compared to traditional APUF. The core area feature size is 93,018F² which is more than sixfold reduction to the voltage-based PUFs. Furthermore, the proposed PUF generates twice the number of challenge-response pairs by sampling the rising and falling edges. It also exhibits a superior resistance against machine learning attacks compared to APUF, making it a better alternative.

With the widespread use of electric vehicles, the large disturbance caused by the uncertainty of the AC side of the power grid will adversely affect the voltage stability of the DC side of the charging pile, which will threaten the charging safety of electric vehicles. In order to achieve fast and adaptive DC voltage regulation under large disturbance, this paper proposes a dual active bridge (DAB) converter control strategy based on Kalman Filter (KF) and Model Predictive Control (MPC). The improved Euler method is used to obtain a more accurate DAB discrete model, and the MPC control system is designed to improve the control accuracy. The best observation results of KF are used as feedforward compensation to improve the accuracy of output voltage regulation and ensure the stability of electric vehicles in the face of various disturbance problems. Finally, the effectiveness of the control strategy is verified by experiment.

In modern surgery, microwave surgical energy devices are used for hemostasis and anastomosis. However, elongated heating region called backward heating distributes around the feeding line, and potentially causes undesirable heating to non-targeted, normal tissue. In order to suppress the backward heating, we considered use of a sleeve with microwave device. Large sleeve inner diameter is required to use the sleeve effectively. However, small sleeve inner diameter is preferable for use in surgery. In this study, numerical analyses were performed to investigate the optimum sleeve inner diameter. The results indicated over 4 mm inner diameter could suppress the backward heating.

Globally-coupled low-density parity check (GC-LDPC) codes have shown great application potential in the error correction of NAND Flash memories. However, the existing LDPC encoder architectures cannot fully use the structure characteristic of GC-LDPC codes. In this letter, focusing on the particular globally-coupled structure, we propose a memory-efficient multiplex-parallel GC-LDPC encoding method and corresponding efficient GC-LDPC encoder architecture. By reusing the local submatrices and optimizing the operation order of piecewise parity bits, the proposed encoding method has low storage overhead and encoding complexity. Then, based on the designed extended shift-register-adder-accumulator (E-SRAA) unit and barrel shifter, we optimize the operator scheduling of the proposed GC-LDPC encoding method when its local encoding is different. The implementation results under various FPGA technologies show that the proposed GC-LDPC encoder architecture achieves a markedly higher throughput-to-resource overhead ratio than existing similar LDPC encoder architectures. Meanwhile, it can meet the bandwidth requirement of ONFI 6.0.

A geometric structure model method has been proposed to provide more non-isolated step-up DC-DC converters and improve the existing topology derivation methods. Based on the three existing DC-DC converters, a geometric structure model is constructed. According to different connection relationships and components represented in the model, ten new high step-up converter topologies are derived. A group of topologies consisting of four DC-DC converters is taken as an example, and a superior converter, namely the high-boost switching inductor converter, denoted as HB-SL converter, is obtained through characteristic comparison. Furthermore, the voltage gain, voltage stress and component parameter design criteria of HB-SL converter are given, and the effectiveness of HB-SL converter is verified by experiments.

An E-Band three-stage power amplifier (PA) in 40nm CMOS is presented in this paper. Since the significant difference in two sides’ impedance, the transformer for matching is difficult to achieve. To address that issue, a transform process is proposed for the transformer. The high peak power-added efficiency (PAE) design and the meticulous layout deployment are applied for a good performance. With a supply voltage of 1.1V, this PA achieves a power gain of 25.3dB with the 3-dB gain bandwidth of 11.2GHz (71.8-83GHz), a saturated output power of 13dBm, and a peak PAE of 25.7% at 76GHz with power dissipation of 79.2mW. The whole core size is only 0.52×0.14mm².

This paper proposes a self-biased sub-threshold CMOS voltage reference for ultra-low-power application. In the current generation path, a source degeneration active load (SDAL) is added to reduce the variation of the reference current (I_R) which helps to produce a stable voltage reference (V_REF). Moreover, by utilizing the line sensitivity (LS) improving circuit, the dependence of V_REF on the supply voltage (V_DD) can be largely reduced. The proposed design is fabricated in a standard 0.18-µm CMOS process. 11-chip measurement results show the prototype design can provide an 147.1mV average voltage with a minimum power consumption of 353pW at 27°C. The line sensitivity (LS) is only 0.014%/V, while the power supply rejection ratio (PSRR) at 10Hz is -68dB. The average temperature coefficient (TC) is 72ppm/°C from -20°C to +80°C, and the die area is only 0.0019mm².

This letter presents a broadband ECL static divider using a 0.8-µm InP DHBT process. The differential implementation of f_t doubler has been employed to extend the bandwidth at the cost of little increase in power dissipation and chip area. The frequency characteristics of the f_t-doubler circuit were analyzed. The chip area was 0.47mm*0.44mm and the total power dissipation was 417mW from dual power supplies of -3.5V and -2.5V. The measurement result shows that the frequency divider can operate from 2GHz to 66GHz for sinusoidal input signal. The input reference SOF (self-oscillation frequency) is 59GHz. The output power locates in 0.41-10.35dBm. This divider can operate within a frequency range of 2GHz to 66GHz, exhibiting a 0.4-f_t frequency range.

To ensure overcurrent protection, fast dynamic performance and good robustness, a novel speed regulation controller is proposed. The interconnection and damping assignment passivity-based control (IDA-PBC) of Port-controlled Hamiltonian (PCH) systems has the advantages of simple structure and explicit physical meaning. On account of fast dynamic performance and q-axis current-constraint are contradictory, this paper presents a current-constraint speed regulation method for the permanent magnet synchronous motor (PMSM) based on port-controlled Hamiltonian (PCH) realization and deep deterministic policy gradient (DDPG) to balance them. First, a modified IDA-PBC controller with integral action (IA) is constructed, which can regulate the speed and the current of the PMSM simultaneously, and be more suitable for practical applications due to the addition of IA. For both current-constraint and fast dynamic performance, the reinforcement learning of DDPG is utilized to find the optimal parameters of the controller. Finally, experiments are carried out to verify the effectiveness and robustness of the method.

The continual switching activity of the switching converter generates electromagnetic interference (EMI) within the system. Single-stage active EMI filters (AEFs) are ineffective at suppressing EMI, whereas multistage active filters are cumbersome and intricately designed. This paper proposes a multi-current injection active EMI filter (MCI-AEF) that incorporates feed-forward and feed-back techniques to address these issues. The results indicate that this filter suppresses EMI more effectively than a single-stage filter of comparable dimensions.

This paper aims to achieve miniaturization of a broadband high-performance microwave component through SIP integrated technology. The circuit design adopts a wide instantaneous bandwidth frequency conversion scheme and sufficient heat dissipation design to ensure the performance and stability. The design of microwave components has 4 GHz instantaneous wideband with the operating frequency band covering Ku band. The system in a package (SIP) receiver includes three layers with independent circuit units. Each layer of circuit is composed of chips, ceramic substrate, and metal block. Each layer of the circuit is designed to be air-tight through a metal cover plate. The structure bearing, signal interconnection and heat conduction of the upper circuit are realized through ball grid array (BGA). The X-ray photos demonstrate that this 3D stacked structure has good and uniform linking characteristics, improving the robustness of the components. The temperature test results show that the temperature remained stable under 45°C after 10 minutes, indicating the efficient heat dissipation design of the device. The test results show that the noise figure is less than 7.0dB, spur and harmonic is less than -50dBm, power consumption is 5.7W, channel phase stability within 4GHz is less than 5°, and switching response time is 45ns.

This paper presents a comparator noise extraction and compensation technique for accuracy enhancement utilized in 16-bit 1MS/s fully-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC). Usually, 14.0-bit ENOB is easily achieved through capacitor mismatch and harmonic calibration. To decrease the noise further, comparator noise extraction technique which statistically estimates the comparator residue voltage is presented. All the measurement and correction process are on chip and in foreground. This technique is verified in a 0.18-µm 5V CMOS process, and it measures a 2.6dB SNR improvement and finally a 94.6dB SNR is achieved with 1MS/s sample clock and a 10kHz input tone.

Improving the modulation bandwidth of an electro-absorption (EA) modulator was demonstrated numerically by applying an optical pre-emphasis utilizing photon-photon resonance (PPR). By integrating an EA modulator within the laser cavity and by simultaneously modulating the modulator and laser’s active section, the PPR effect contributed to the improvement in the bandwidth of the modulator. The 3-dB bandwidth of the laser diode integrated with an EA modulator inside the cavity showed a very wide modulation bandwidth of more than 200GHz thanks to the optical pre-emphasis effect utilizing PPR even though the EA modulator had a modulation bandwidth of less than 100GHz.