A synthesizable spread spectrum clock generator based on type-II/III fractional-N DPLL

Abstract

This paper presents a fully synthesizable spread spectrum clock generator (SSCG) based on a fractional-N Digital PLL (DPLL). The designed SSCG adds a triangular digital signal to the frequency control word (FCW) to down-spread the frequency of the clock signal and reduce its electromagnetic interference (EMI) to near signals. Because of the linear frequency modulation of the triangular signal, the designed DPLL can be configured to operate in a Type-III mode to track the frequency variation more accurately than a Type-II setting. A proof-of-concept prototype was built using a 65nm CMOS technology. The measured EMI reduction because of the SSCG operation was 22.0dB. The designed SSCG is based on a fractional-N DPLL, which gives a 1.0GHz signal from a 100MHz reference frequency and consumes 4.83mW and 3.1mW from a 1.2V DC supply in the fractional and integer mode of operation, respectively. The measured rms jitter of the designed prototype was 3.95ps and 2.1ps in the fractional and integer modes of operation, respectively. The core area of the developed prototype is 0.1mm².