Ultrahigh framerate vision chip featuring central-based edge detection processed by all-digital in-imager global-parallel processing architecture

抄録

Vision chip plays an important role in artificial intelligence (AI) image processing. In-imager global-parallel processing architecture (IIGP) demonstrates considerable promise for ultralow latency at both circuit and system levels towards vision chips that demand high processing speed. However, functionality such as edge detection of previous IIGP work is limited because of the bottleneck of processing multibit precision multiplication and accumulation operations (MACs) in a binary architecture. To address this bottleneck, this paper proposed a 32×32 pixels ultrahigh framerate vision chip that features central-based edge detection (CBED) processed by the all-digital IIGP architecture. The SPICE simulation results show that the proposed circuit achieves an ultrahigh framerate of 5.56Mfps, which is 2.16× compared to the state-of-the-art in/near-imager vision chip work when processing edge detection functionality, marking a significant advancement in high-speed image processing.