Design and implementation of IDELAY-RO PUF in Xilinx ZYNQ PSoCs

Abstract

This paper presents a compact IDELAY-based PUF technology, which utilizes Xilinx FPGA IO-Block’s IDELAY tap delay values to generate a unique and secret key. IDELAY-RO generates a counting-pulse input by replacing the inverters in the Ring Oscillator (RO) and developing it over a fixed time to produce a corresponding dataset in ZYNQ PSoC’s Programmable Logic (PL). Polynomial regression is fitted to the dataset and compared with the raw data to create a 31-bit bitstring in the Processing System (PS) of ZYNQ PSoC. Our analysis of thirty XC7Z010CLG400-1 chips revealed that the IDELAY-RO PUF has a reliability of 98.23% and uniqueness of 49.63%, with 59.38% uniformity, using fewer FPGA resources.