In order to study the coupling mechanism of the transient immunity of digital control circuits, the equipment of digital control circuits is developed in order to obtain a general method of modeling and simulation of the transient immunity. The power module of the digital control circuit is its basic function module. This paper extracts the characteristic parameters of the EMI coupling path of the digital control circuit and establishes an equivalent circuit, based on the established RFI-based power module conductive immunity model. A method of port response simulation for power module of digital control circuit under transient interference based on transfer function and segmental circuit simulation is proposed. This method has a certain value for studying the coupling mechanism of conductive interference.

Homomorphic Encryption (HE) has become a promising technique to protect the data privacy in cloud computing, while its slow speed highly restricts the application. We propose a high throughput and fully pipelined implementation of ciphertext multiplier on FPGA to accelerate ciphertext multiplication, which is one of the frequently performed operations in HE applications and takes most of the calculation time. The fully pipelined architecture avoids memory access conflict and minimizes the memory usage on chip. Consequently, the logic cells, including LUTs and DSPs, are efficiently utilized for high parallelism degree and high throughput is achieved. The throughput is increased to 4.7 times compared to state-of-art FPGA designs and 1340 times of CPU performance.

A low-dropout voltage linear regulator with low quiescent current and high PSR over a wide frequency range is designed to meet the application requirements of high-performance CMOS image sensor. An embedded impedance attenuation buffer is proposed to embed the feedforward path into the buffer, reduce the quiescent current and improve PSR in a wide frequency range. The simulation result shows that LDO achieves a PSR better than 60dB up to 10MHz for load current up to 100mA. The LDO achieves 65dB PSR at 1MHz and 90dB PSR at 1KHz. LDO consumes a quiescent current of 36uA with a bandgap reference circuit included.

This paper presents a compact IDELAY-based PUF technology, which utilizes Xilinx FPGA IO-Block’s IDELAY tap delay values to generate a unique and secret key. IDELAY-RO generates a counting-pulse input by replacing the inverters in the Ring Oscillator (RO) and developing it over a fixed time to produce a corresponding dataset in ZYNQ PSoC’s Programmable Logic (PL). Polynomial regression is fitted to the dataset and compared with the raw data to create a 31-bit bitstring in the Processing System (PS) of ZYNQ PSoC. Our analysis of thirty XC7Z010CLG400-1 chips revealed that the IDELAY-RO PUF has a reliability of 98.23% and uniqueness of 49.63%, with 59.38% uniformity, using fewer FPGA resources.

We are concerned with the numerical simulation of metasurfaces modeled by generalized sheet transition conditions (GSTCs). A hybridizable discontinuous Galerkin (HDG) method is pro-posed to treat the field discontinuity on the metasurface. We briefly recall the mathematical expressions of the surface susceptibility tensors and present the formulations of the HDG method. The numerical examples by simulating monoanisotropic metasurface show that the proposed HDG method can easily adapt to the discontinuities caused by GSTCs. Additionally, we present COMSOL simulation results for the same metasurface to further validate the efficacy of the proposed method.

A novel miniaturized fourth order Hilbert fractal rectifier antenna for collecting ultra-short wave RF electromagnetic energy is proposed. The receiving antenna is miniaturized by using the fourth-order Hilbert fractal structure and the slow-wave cross-finger structure, with antenna sizes of 274.86mm × 144.38mm, seven resonances are excited and form a wideband, which locates at 100-300MHz. In the rectifier part, the third order voltage doubling rectifier circuit is designed, which is composed of three sets of Schottky diodes and filter capacitors. The maximum rectification efficiency of this circuit is greater than 80% in simulation and 78% in measurement. The experimental results show that the rectifier antenna has great potential to collect energy in the electromagnetic environment with abundant ultrashort wave energy.

In this paper, a novel design of an ergodic sequential logic cochlear single partition model, which can reproduce a typical nonlinear sound processing function (so-called nonlinear compression) of a mammalian cochlea, is proposed. Analyses show that the model can reproduce fundamental characteristics of the nonlinear compression of the mammalian cochlea. In addition, the model is implemented by a field programmable gate array, and its operation is verified by experiments. It is then shown that the model can be implemented with fewer circuit elements and consumes lower power compared to a standard ordinary differential equation cochlear model. Finally, it is discussed that the results of this paper will be useful in developing a small and low-power cochlear implant that can reproduce nonlinear sound processing functions of the human cochlea.

This paper proposes a novel quadratic boost converter (QBC) based ultra-high gain DC-DC converter with coupled inductor (CI) and voltage multiplier cells (VMC). Based on the structure of this converter, the energy leaked through the coupled inductor can be recycled and transferred to the output to improve the voltage gain. Meanwhile, it has the common ground characteristics and good static output stability. The converter is tested for an application requiring the output power of 50W∼300W, operating with 25V input voltage and 547V output voltage, and it has the voltage gain of 21.8 under the medium and low duty cycle, the peak efficiency is 92.5%.

This paper proposes a methodology to design broadband high-efficiency power amplifiers. A novel continuous mode is proposed through combination the continuous class-F mode and the traditional class-EF mode under certain conditions. Thus, the advantages of wide bandwidth and high efficiency can be integrated into one power amplifier, that is, the proposed continuous mode class-EF power amplifier mode. In order to verify the effectiveness of the proposed method, a broadband high-efficiency power amplifier operating at 1.5-3.0GHz is designed and implemented based on the CGH40010F GaN transistor. Measurements indicate that the saturated output power is greater than 40.2dBm, drain efficiency is between 63% and 70%, gain exceeds 10dB, across the whole frequency range.

Piezoelectric transducers (PZTs) can be used not only for vibration energy harvesting (VEH), but also for vibration signal sensing. However, it is difficult to realize both functions on a single PZT. In this paper, we propose a simultaneous energy harvesting and acceleration measuring (SEHAM) solution based on a single PZT. It is implemented by time-space sharing strategy rather than time-division multiplexing strategy. In addition, a signal extraction model based on first harmonic approximation (FHA) method is established to recover acceleration signals from SEHAM operations. Finally, a rapid prototype is built to evaluate the performance of SEHAM under different vibration frequencies. Experimental results show that the EH and AM operations can be carried out simultaneously. At the resonance point, the average relative error of AM is 7.14%, and the EH power is 189.10µW with a PZT open-circuit voltage of 5V. This solution is significant to the development of self-powered sensors and can be used as redundant backup of traditional sensors.