PDN analysis of 3D chiplet integration with a DC-DC converter on active interposer

Abstract

The rapid evolution of data-intensive applications has increased the demand for multiple power levels and higher current in electronic systems, challenging the efficiency and stability of power supplies. This paper addresses these challenges by investigating the performance of power distribution networks (PDN) in 3D chiplet architectures. We established and validated an RLCG model for the active interposer interconnection path. Utilizing this model, we analyzed the PDN performance for both on-board voltage regulator modules (VRM) and on-interposer direct current to direct current (DC-DC) scheme. Comparative analysis reveals that the on-interposer DC-DC scheme PDN significantly reduces overall impedance and lowers IR-drop. The study also explores the effects of design elements like bump quantities and decoupling capacitors (de-caps) on PDN efficiency. Further, the practical application based on our findings is demonstrated through the successful implementation of a forwarding chip with on-interposer DC-DC converters.