The laser power transfer (LPT) system is one of the most promising systems in the long-rang wireless power transfer field. An interesting extension of LPT technology is the combination with optical communication. However, traditional optical communication technology for LPT system suffers from crosstalk issue, which leads to instability of power transmission and inaccuracy of data decoding in practical application. In this paper, a data modulation method is proposed to guide the modulation process of laser input current. Thus, the data can be directly incorporated into the optical power delivery path without inducing power fluctuation at receiver. Furthermore, based on the proposed data modulation method, a laser power supply consisting of a constant-current converter and a bidirectional converter is employed. It is possible that the desired modulated laser input current may be affected by the laser input voltage due to the bandwidth limitation of the laser power supply. Thus, a feed-forward scheme is also introduced to ensure the laser power supply can output desired modulated current. Finally, the experimental results are shown to validate the theoretical analysis.

High-density interconnects in modern PCBs, especially in DDR5 technology, have exacerbated near-end crosstalk (NEXT) and far-end crosstalk (FEXT), degrading signal quality. In this research, proposed Periodical Spiral Resonators (PSRs) within signal lines to mitigate these issues. The spiral structure extends and twists signal paths, increasing electrical length and altering the electric field distribution, reducing mutual coupling between traces. Experimental validation shows significant signal quality improvement up to 10 GHz, with a 22.35 dB reduction in NEXT and 30.16 dB reduction in FEXT. Simulations reveal a 50.47% reduction in near-end crosstalk and an 87.72% reduction in far-end crosstalk when compared to existing techniques. Our approach holds immense potential for DDR5 memory modules, promising minimal NEXT and FEXT, and ensuring superior performance and reliability.

The rapid evolution of data-intensive applications has increased the demand for multiple power levels and higher current in electronic systems, challenging the efficiency and stability of power supplies. This paper addresses these challenges by investigating the performance of power distribution networks (PDN) in 3D chiplet architectures. We established and validated an RLCG model for the active interposer interconnection path. Utilizing this model, we analyzed the PDN performance for both on-board voltage regulator modules (VRM) and on-interposer direct current to direct current (DC-DC) scheme. Comparative analysis reveals that the on-interposer DC-DC scheme PDN significantly reduces overall impedance and lowers IR-drop. The study also explores the effects of design elements like bump quantities and decoupling capacitors (de-caps) on PDN efficiency. Further, the practical application based on our findings is demonstrated through the successful implementation of a forwarding chip with on-interposer DC-DC converters.

A 10-bit 500 kS/s successive approximation register (SAR) analog-to-digital converters (ADCs) in 40-nm CMOS technology is presented in this paper. To reduce the power consumption of capacitive digital-to-analog converter (CDAC), a novel energy-efficient switching scheme is proposed without capacitor-splitting structure and additional V_aq reference. Considering the reset energy of 0.249 CV²_ref, 94.93% switching energy saving and 75% total capacitor number reduction are achieved over the conventional switching technique. And the common mode voltage converges back to around V_cm by single-side switching up and then down. Furthermore, a low-power comparator is proposed based on the conventional double-tail architecture. The addition of the cross-coupled transistors avoids the unnecessary discharging of the pre-amplifier stage, decreasing 16.3% power consumption over the conventional architecture. Post-simulation results show the peak DNL/INL are +0.79/-0.28 LSB and +0.61/-0.57 LSB respectively. At 0.7 V supply, the proposed SAR ADC achieves an SNDR of 57.9 dB and an SFDR of 75.4 dB with Nyquist frequency. And the overall power consumption is 0.9047 μW, leading to a Walden’s figure of merit (FOM_W) of 2.8 fJ/conversion-step.

This paper focuses on an on-chip integrated frequency-domain temperature sensor using a 0.18 μm CMOS process. Programmable load delay units and power feedback pulse width modulation technology are employed to reduce errors caused by process variations and power supply non-idealization. In detail, this paper uses a power average feedback modulator (PAFM) to detect changes in the power supply by converting the supply voltage into a fixed periodic pulse with varying duty cycle. In addition, the quantization time of the frequency digital conversion module is adjusted linearly, effectively reducing the power sensitivity of the temperature sensor from 0.0809°C/mV to 0.0099°C/mV. The sensor shows a measured inaccuracy of -0.66°C to +0.68°C from -70°C to 120°C, and occupies a compact area of 0.022 mm².

This article introduces a novel, compact 12-bit column driver DAC for LED on Silicon (LEDoS) displays using HLMC 55 nm process. The proposed DAC utilizes fewer switches by introducing a multi-level strategy to transform signals, with its complete nonlinearity. This novel DAC operates within an output voltage range of 0.2-4.8 V, achieving a LSB of 1.1 mV. Simulation results indicate maximum differential nonlinearity of 0.22 LSB and integral nonlinearity of 0.54 LSB. Under a load of 15 KΩ resistor and 15 pF capacitor, the circuit achieves a settling time of 2.4 μs. It is suitable for Augmented Reality (AR) display devices with high color depth and resolution.

An alumina ceramic based U-shaped slot nested re-transmitting chipless tag temperature sensor is proposed in this paper. The U-shaped nested slots are etched in the conductive layer of the top layer of the alumina ceramic. The dielectric constant of the alumina ceramic increases monotonically with temperature increase which leading to change in the resonance frequency of the U-shaped slot to produce the frequency shift. This sensor comes with an ID feature that allows for coded identification. The temperature sensing sensitivity achieves 0.5211 MHz/°C. This temperature sensor has the characteristics of high temperature sensitivity, small size, passive, and the ability to measure temperature wirelessly over long distances. It has certain application potential in the field of high-temperature wireless sensors.

This paper presents a gain enhancement technique for a Common-Gate Feedforward Transimpedance Amplifier (CGFW TIA). The proposed CGFW TIA achieves gain improvement through a current injection technique and an additional feedback path. It is designed using a 0.18-μm CMOS technology. Post-layout simulation results show that the proposed CGFW TIA improves the transimpedance gain by 1.76 times without an increase in power consumption compared to conventional designs.

The signal acquisition and processing module, as a crucial component, is essential for achieving high-performance radar receivers. In this paper, based on key chips such as ADC, FPGA, MCU, clock, and ethernet, a multi-functional high-dynamic intermediate-frequency (IF) signal acquisition and processing module is designed. This module adopts optimized ADC analog front-end design, high-performance clock distribution, and data reception with preprocessing technology, effectively enhancing the dynamic performance of the acquisition module. Additionally, by utilizing MCU in conjunction with Ethernet communication, remote access debugging and program updates for the acquisition module are achieved, providing convenience for engineers to conduct remote maintenance in complex environments. Furthermore, functionalities such as power detection, fault detection, channel gain control, and high-speed data transmission are integrated, expanding the module’s application potential. Through practical tests, the IF signal acquisition module demonstrates a signal-to-noise ratio greater than 70 dB, a spurious-free dynamic range greater than 80 dB, an effective number of bits greater than 11.5 Bits, and total harmonic distortion less than -80 dB, meeting the application requirements of ground detection radar and shipborne radar.

With the advancement of integrated circuit technology, the stable operation of electronic devices is crucial. Targeting the issue that traditional analog circuit fault diagnosis models cannot simultaneously satisfy noise resistance, stability, and accuracy in real circuit environments, this research represents an analog circuit fault diagnosis model relied on the whale optimization algorithm and an improved SDAE. The model transforms fault signals into 2D time-frequency representations using VMD and CWT to achieve initial denoising; Utilizing DSDAE for further denoising and dimensionality reduction of feature vectors; finally, RF is used for classification. The results of the simulation demonstrate that even in noisy conditions, the model can maintain excellent diagnostic accuracy and stability. making certain improvements in enhancing the operational reliability of electronic devices.