IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Design of hierarchical cache coherence protocol based on Chiplet architecture
Jianghua GuiBing LiTongtong GuoAnzhou LaiShuaishuai Zhang
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JOURNAL FREE ACCESS

2025 Volume 22 Issue 12 Pages 20250219

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Abstract

This paper proposes a directory-based hierarchical cache coherence protocol for highly scalable Chiplet architectures. The proposed protocol can be seamlessly divided into two independent levels, the first level handling the inter-core cache coherency within a single Die while the second level dealing with the intra-Die cache coherency across multiple Dies. The proposed protocol is implemented using a two-level directory structure which exhibits superior scalability in terms of storage overhead. Simulation results indicate our approach using a two-level directory structure reduces the miss rate of the shared last-level cache (LLC) as compared to conventional approach using a single-level directory structure. This reduction enhances overall cache performance as the average memory access latency is reduced.

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© 2025 by The Institute of Electronics, Information and Communication Engineers
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