In this letter, a rasorber with an ultra-wide electromagnetic (EM) wave absorption bandwidth is proposed, which is composed of multiple layers of indium tin oxide (ITO) resistive films with different structures and a metal ground. The rasorber has an absorption rate of over 90% at 1 GHz-21.2 GHz under different polarized waves vertically incident, with a relative bandwidth of 182%. When EM waves are obliquely incident, it can maintain an absorption rate of over 80% in the range of 45° under TE and TM polarization, with angular incidence stability. An improved genetic algorithm was used to optimize the rasorber performance during the design process. An array prototype of the proposed structure is fabricated for testing and the experimental results match the simulation. The proposed rasorber belongs to EM metamaterials, with a cell period size of 0.167 λ_L and a thickness of 0.1 λ_L, offering advantages in miniaturization and low-profile.

This paper reports a waveguide for terahertz electromagnetic wave transmission, featuring a complex multilayer stepped bend waveguide. The waveguide was fabricated on a silicon wafer using deep reactive ion etching, which had better mechanical performance compared to Silicon-On-Insulator based etching. After etching, the wafer underwent gold plating, low-temperature bonding, and dicing to produce the silicon waveguide, overcoming the integration challenges and slow processing of metal based waveguides. The experimental work focuses on investigating the key fabrication parameters that influence the waveguide’s transmission performance, as well as optimizing the Bosch process for etching the multi-layer stepped structure. Finally, an analysis was conducted on the differences between the measurement and simulation results. Results showed that the insertion loss of the waveguide was about 0.5 dB within the 300-530 GHz, achieving low-loss terahertz electromagnetic wave transmission.

This article presents a 100 Gb/s four-level pulse amplitude modulation (PAM4) analog front-end (AFE) implemented in TSMC’s 28-nm CMOS process. The continuous-time linear equalizer (CTLE) employs the transconductance (GM) stage for mid-frequency (MF) peaking, while leveraging the transimpedance (TIA) stage to produce high-frequency (HF) peaking. This allows the HF peak frequency to remain constant as the boost range is adjusted. While the variable gain amplifier (VGA) employs shunt inductive peaking and feedforward technique to extend bandwidth. Both CTLE and VGA use complementary structures to improve linearity. Frequency response tests show the AFE has a 31 GHz peak frequency and a 33.1 dB gain boost. Eye diagram measurements confirm it can open eyes for 100 Gb/s PAM4 signals.

The globalization of the semiconductor supply chain has created new challenges for security researchers. Hardware Trojans (HTs) are considered to be one of the most difficult challenges. This paper presents an effective HT detection method based on power side-channel features that can classify circuits under test (CUTs) into Trojan-inserted (TI) and Trojan-free (TF). It classifies the power traces based on the machine learning algorithms. The selected machine learning algorithms include supervised and unsupervised algorithms. The experimental results demonstrated on AES benchmarks show that the accuracy of TI power traces is 91.38% and 65.81% with supervised and unsupervised machine learning, respectively. Finally, it uses majority voting to perform the secondary classification on the CUTs based on the classification results of the power traces, which can mitigate the effects of process variations and noise. The experimental results show that the secondary classification can achieve 100% and 94.44% accuracy of TI circuits with supervised and unsupervised machine learning, respectively. The effect of dataset balance on machine learning performance was investigated, and a balanced dataset can improve accuracy by 13% to 30%. The experimental results on AES 8/128-bit HT demonstrate the effectiveness of the proposed method in detecting unknown Trojans.

Power obtained from ultra-small energy harvesters is often tiny and difficult to use. The circuits with high power consumption can be driven by temporarily storing that power in a capacitor for a long time and discharging it instantaneously. We propose a unique intermittent-drive CPU that can operate even if the supplied power is minimal and intermittent. Regular CPUs are reset when power is turned off, so they are reset after every intermittent drive. This is because the regular CPU assumes a stable power supply. To enable intermittent and low-power operation, the amount of power required for CPU operation consumed at one time is reduced by executing only one CPU instruction cycle at a time. After instruction cycle processing, only the information necessary to continue the operation is stored in nonvolatile memory and read back when needed in subsequent cycles. This method does not save all data simultaneously, as in the sleep operation, but saves the data by dividing it frequently. Therefore, it has the advantage of low instantaneous power consumption and does not require special devices such as nonvolatile Flip Flops. We implemented an intermittent-drive CPU using the RISC-V RV32I instruction set architecture on an FPGA and a chip fabricated in a 0.18 um standard CMOS process. The designed chip was intermittently driven successfully with 6 kHz power and reset signal.

This paper presents a 6 bits 10 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing a multi-conversion dynamic amplifier (MC-DA) to enhance power efficiency. The MC-DA enables voltage-time conversion on both rising and falling clock edges, reducing clock frequency and dynamic power consumption. A shoot-through prevention (STP) latch ensures accurate conversions, while a reset generator accelerates reset times, improving throughput. A dual-ring counter-based clock generator optimizes phase alignment. Measurement results from a 0.5 μm CMOS implementation show a signal-to-noise and distortion ratio (SNDR) of 34.52 dB and a spurious-free dynamic range (SFDR) of 43.08 dB. The proposed ADC achieves significant power savings, making it suitable for low-power applications.

Digital cancellation is a key method for interference suppression in communication systems but it fails under receiver saturation. This paper proposes a novel signal folding-based interference cancellation architecture to prevent signal clipping caused by dynamic range overflow. We then combine the folding method with stochastic logic to reduce hardware costs, addressing the bottleneck of traditional stochastic computation where adders, rather than multipliers, limit performance. A new stochastic adder enables signal folding in the probability domain, which facilitates efficient interference suppression. Measurement results demonstrate that the proposed design reduces delay by at least 52.4% and lowers hardware costs by 59.6% compared to conventional approaches.

With the widespread use of analogue circuits, current reference (CR) trimming has become an increasingly important issue. Therefore, finding a reliable and area-efficient trimming method becomes more and more critical. In this paper, a novel area-efficient memristor-based trimming circuit for current reference (CR) with temperature coefficient optimization capability is proposed. The proposed trimming core circuit uses only the source-degraded current mirror embedded in the memristors, thus achieving a significant area reduction. The circuit produces an output of approximately 5.2 μA, and test results show a calibrated output temperature coefficient (TC) of less than 75 ppm/°C over the temperature range of -20°C to 120°C, with a linearity of 4.3%/V over 2.2 to 4 V. The circuit implementation uses 0.18-μm CMOS technology. The layout area is less than 0.0016 mm², representing average area savings of 84.3% over the current state of the art in trimming circuits.

The conventional FCS-MPC operates by selecting a switching state per control cycle through cost function optimization. However, it is possible for this method to consistently select the same switching state, resulting in high THD and switching frequency variability. This paper proposes a modified FCS-MPC with fixed switching frequency for voltage source inverters (VSIs) based on conditional suboptimal switching. When the optimal vector matches the previous one, the vector that sub-optimizes the cost function is selected. Simultaneously, a duty cycle modulation scheme applies to this suboptimal state via time-modulated actuation. The proposed strategy reduces THD while fix the switching frequency. Hardware experiments are conducted to verify the effectiveness of the proposed strategy.

This paper proposes a directory-based hierarchical cache coherence protocol for highly scalable Chiplet architectures. The proposed protocol can be seamlessly divided into two independent levels, the first level handling the inter-core cache coherency within a single Die while the second level dealing with the intra-Die cache coherency across multiple Dies. The proposed protocol is implemented using a two-level directory structure which exhibits superior scalability in terms of storage overhead. Simulation results indicate our approach using a two-level directory structure reduces the miss rate of the shared last-level cache (LLC) as compared to conventional approach using a single-level directory structure. This reduction enhances overall cache performance as the average memory access latency is reduced.

This paper presents a high-speed single channel reconfigurable successive approximation register (SAR) analog-to-digital converter (ADC) for ultra-high-speed system. The ADC operates in two modes: 1 GS/s 8-bit and 1.5 GS/s 6-bit. A floating-skip algorithm is proposed to address the speed limitation and amplitude attenuation of input signals in 6-bit operating mode, while avoiding unnecessary switching power consumption. Meanwhile, the ADC employs binary redundant CDAC to improves the fault tolerance range and relaxes the requirements for setting accuracy, further achieving high conversion speed. The reconfigurable ADC is designed in the 28-nm CMOS process, it achieves the 36.69-/47.68-dB signal-to-noise-and-distortion ratio (SNDR) at 1-/1.5-GHz sampling rate with the same power consumption of 4.42 mW. The ADC core occupies an active area of only 0.003948 mm². It achieves a FoMw of 22.31 fJ/conv.-step at 8-bit conversion mode.

This letter presents a C-Ku-band high-efficiency power amplifier (PA) fabricated using 0.25 μm gallium nitride (GaN) high electron mobility transistor (HEMT) technology. A novel bias network criterion, which quantifies the bandwidth-efficiency tradeoff and is used to improve the high-band efficiency, is thoroughly discussed. The partial harmonic control amplification cell (PHCAC) design method is applied to obtain the optimum source and load impedances for each transistor in the PA’s output stage at both fundamental and second harmonic frequencies, thereby enhancing the mid-band efficiency. In addition, the intrinsic PAE of the transistor is sufficiently high at low frequencies, resulting in a higher overall efficiency. The proposed 7-13 GHz high-efficiency GaN PA MMIC delivers an average output power of 42.1-43.3 dBm (16.2-21.3 W) with a power-added efficiency (PAE) of 38%-43% and a gain of 30.7-32.9 dB under a drain voltage of 28 V. The proposed GaN PA MMIC occupies an area of 13.1 mm²

Self-feedback test vector generation uses the circuit itself to generate test vectors, which greatly reduces the cost of testing without relying on other equipment. However, there are a great number of feedback nodes in the circuit, so how to select the feedback scheme is a problem. This paper proposes an adaptive matching method to select the self-feedback scheme. First, the final feedback nodes are selected by using the self-defined test vector similarity in the adaptive matching method, and then the optimal arrangement order of feedback nodes is determined by using the self-defined test vector matching degree. The self-feedback structure of the sequential circuit is improved and the number of multiplexers (MUXs) is reduced. The test vector similarity and the test vector matching degree are introduced into the parameters TR and Cr of the Spider Wasp Optimization Algorithm (SWO), respectively, so that the parameters can be adaptively adjusted in the process of selecting feedback nodes.

Detecting hardware Trojans (HTs) in mixed-signal circuits is challenging due to structural complexity and cross-domain vulnerabilities between analog and digital components. Existing methods often rely on post-silicon analysis, circuit modifications, or focus solely on leakage, limiting practicality. We propose HGAT4TJ, a pre-silicon detection approach based on heterogeneous graph attention networks, which models gate- and transistor-level structures in a unified graph. This enables effective cross-domain HT detection directly from netlists without requiring golden models. Experimental results on benchmark circuits indicate that HGAT4TJ achieves 100% detection rate at the circuit level and over 97% accuracy at the node level, making it a non-invasive solution for HT detection in mixed-signal circuits.

This paper proposes a background digital calibration technique for high-speed multi-channel time-interleaved ADCs (TI-ADCs) to address sub-channel memory nonlinearities and inter-channel mismatch errors. The method employs a simplified DDR-based Volterra series model with reduced parameters. An improved Input-Free Band (IFB) error detection scheme eliminates the need for reference channels or test signals, ensuring uninterrupted ADC operation. To effectively overcome non-convex optimization challenges, the proposed approach employs a customized artificial bee colony (ABC) algorithm to extract Volterra kernel coefficients. Validated through simulations and a 1-Gsps 14-bit 2-channel PI-SAR ADC prototype, the technique demonstrates effective compensation for subchannel memory nonlinearities and inter-channel first-order mismatches, achieving SFDR improvements of 11.67-24.69 dB across input frequencies. The fully-digital solution offers versatility and portability for diverse ADC architectures.