A dither-based background calibration circuit for pipelined ADCs in 40 nm CMOS

Abstract

This paper presents a circuit implementation of a dual-dither strategy that combines calibration dither and linearization dither to effectively address the correlation between calibration performance and input signal amplitude, while mitigating amplifier output compression and range redundancy caused by multi-level dither injection. Specifically, we propose the ‘Roving Star’ scheme, which generates a multi-bit, uniformly distributed, and uncorrelated dither signal. Additionally, we propose a threshold voltage dithering circuit with a wide-range adaptive adjustment reference voltage to correct residual curve deviation resulting from the mismatch between flash and multiplying digital-to-analog converter (MDAC) reference voltages. These advancements were successfully implemented in a 500 MS/s 14-bit pipelined ADC fabricated with a 40 nm CMOS process. The implementation resulted in significant performance improvements, notably increasing the SFDR from 69.4 dB to 89.2 dB and enhancing the SNDR from 65.6 dB to 70 dB.