A low-power bandgap-free LDO circuit with wide input range

Abstract

This paper presents a low power LDO circuit that can operate with a maximum input voltage of 30V without the need for a bandgap reference. The LDO leverages a combination of an error amplifier and a biasing circuit, allowing for the generation of a stable output voltage solely from the bias current, thereby eliminating the inherent challenges associated with high-voltage references, such as poor PSRR and complex startup mechanisms. The proposed design effectively reduces the circuit’s footprint and power consumption. The implementation is based on a 0.18 μm process. The input voltage range for the LDO is 3.5-30 V, a maximum load current of 1 mA, a dropout voltage of 1.25 V, a power supply rejection ratio (PSRR) of 111 dB, a line regulation of 4.5 μV/V, a load regulation of 6.7 μV/mA, and a power consumption of 1.5 μA.