This paper presents a bandgap reference (BGR) circuit with high precision and low power, which is suitable for wide supply and temperature range DC-DC converters. A thermal compensation method is designed to improve output accuracy. A thermal shutdown detection (TSD) circuit is proposed to prevent overheating. It also adopts a two-channel pre-regulator, which reduces the current consumption and area while enhancing PSRR. The measured results show the temperature coefficient (TC) stands at 5.69 ppm/°C in the range of -40°C to 155°C. The typical current consumption is 0.84 μA in the supply range from 3.5 to 40 V. The PSRR is -86 dB at 1 kHz.

The nerve electrical stimulation is an effective way to treat neuropathic diseases. Normally, the mice are the subjects for neural stimulation. In order to solve the problem of decreasing transmission efficiency and frequency mismatch of wireless power supply during the experiment caused by the movement of the mice, a squirrel cage system based on wireless power transfer combined with temporally interference is proposed in this paper. The low frequency envelope current superimposed by high frequency power supply with small frequency difference is used for nerve electrical stimulation. It is proved by simulation and experiment that the proposed squirrel cage system can generate stable magnetic field in more than 80% area when the operating frequency is 300 kHz.

A novel broadband circularly polarized (CP) all-dielectric transmitarray antenna (TA) in millimeter-wave (mmWave) band is designed using “Hamburger” shaped unit-cell in this paper. A circular contour TA is constructed by optimizing the transmission phase of each unit-cell to realize a specific phase distribution on the TA surface. The proposed TA is fabricated using 3-D printing technology. It achieves a peak gain of 27.8 dBi with an aperture efficiency of 46.7% at 39 GHz, a 1-dB gain bandwidth of 22.1% and a 3-dB ARBW of 21%, respectively.

True random number generator (TRNG) is an essential part of cryptographic systems. In this paper, a high bit rate and self-stable probability TRNG based on spin-orbit torque magnetic tunnel junction (SOT-MTJ) is proposed. The TRNG reaches 16.7 Mb/s bit rate and 93.62 pJ/bit energy consumption for a single cell. In addition, the TRNG achieves a stable probability of random numbers regardless of the voltage and device to device variation. The random bits have passed the National Institute of Standards and Technology statistical test suite. Our results provide a candidate of high bit rate TRNG for IoT security applications.

Due to the dynamic changes in vibration, energy harvesting using Piezoelectric Transducers (PZT) faces challenges with limited harvesting power. Hence, this paper presents a hybrid rectifier with dual-modes Synchronous Electric Charge Extraction (SECE) method for harvesting piezoelectric energy, aiming to achieve a higher output power. In situations where electric energy is insufficient, the rectifier operates in the passive SECE mode, enabling energy harvesting without a power supply and helping to self-start faster. When there is sufficient electric energy, it adaptively switches to the active SECE mode to enhance harvesting efficiency. Measurements indicate that the maximum power harvested in the passive SECE modes can be up to 2 times that achieved with the traditional full-bridge rectifier, and the peak conversion efficiency reaches 83% in the active SECE mode.

This paper proposes a 5-transistor (5-T) voltage reference (VR) with enhanced self regulation for low-voltage and low-power applications. In the proposed circuit, the gate feedback with the source degeneration is applied to a transistor to form the enhanced self regulation to reduce the impact of the supply voltage (V_DD) on the reference voltage (V_REF). Moreover, a stacked gate-source connected transistor further increases the impedance from the V_DD to ground. In this way, both line sensitivity (LS) and power supply rejection ratio (PSRR) can be improved without any additional current overhead. The proposed VR is fabricated in a 0.18 μm CMOS process, while 10 samples have been measured. It can provide a V_REF of 387.1 mV and consume a power consumption of 50.4 pW at 27°C. The results show that the average LS reaches 0.014%/V when the V_DD varies from 0.6 V to 5 V. Additionally, the PSRR is -73.5 dB and -49.4 dB at 10 Hz and 100 Hz respectively. The average temperature coefficient (TC) is 80.8 ppm/°C without any trimming from 0°C to 100°C. The total area of the proposed VR is only 0.0038 mm².

A high-speed and high-slew-rate operational amplifier (OPA) is presented in this paper. The gain boosting circuit is embedded in the circuit in order to improve the open-loop DC gain, which significantly improves the overall gain without adding additional stages and ensures high performance under low supply voltage conditions. In order to meet the demand for fast response in high-speed applications, the slew rate enhancement circuits are proposed to reduce the large signal build-up time of this OPA. Meanwhile, the operational amplifier employs the Ahuja compensation method to improve the phase margin (PM) of the circuit and is able to achieve a higher unit gain bandwidth with a smaller compensation capacitance. The proposed operational amplifier is designed based on TSMC 0.18 μm CMOS process with a chip area of 0.468 mm². Post-simulation results show that the op-amp has an open-loop gain of 111 dB, a unit gain bandwidth of 240 MHz, and a phase margin of 62°. The measured quiescent current is 3.1 mA under the 5 V supply voltage, and the slew rates are 403 V/μs and 386 V/μs with the help of the slew rate enhancement circuits.

This brief presents a power-efficient PAM-4 transmitter. The proposed hybrid voltage-mode current-mode (VM-CM) driver with push-pull current-mode equalization reduces the power consumption. The date-dependent jitter (DDJ) suppressed C²MOS MUX is devised to reduce the output jitter and power of prior widely used C²MOS MUX. The phase aligner is utilized to provide sufficient time margin for the high-speed 4-1 MUX, thus no power-hungry high-speed latches along with its clock buffer are required for retiming. Fabricated in 40-nm CMOS, our prototype can operate at 56 Gb/s data rate with 0.7 pJ/bit energy efficiency and 6.1 dB channel loss at Nyquist frequency of 14 GHz, namely achieving a figure-of-merit (FOM) of 0.11 pJ/bit/dB.

This paper presents a low power LDO circuit that can operate with a maximum input voltage of 30V without the need for a bandgap reference. The LDO leverages a combination of an error amplifier and a biasing circuit, allowing for the generation of a stable output voltage solely from the bias current, thereby eliminating the inherent challenges associated with high-voltage references, such as poor PSRR and complex startup mechanisms. The proposed design effectively reduces the circuit’s footprint and power consumption. The implementation is based on a 0.18 μm process. The input voltage range for the LDO is 3.5-30 V, a maximum load current of 1 mA, a dropout voltage of 1.25 V, a power supply rejection ratio (PSRR) of 111 dB, a line regulation of 4.5 μV/V, a load regulation of 6.7 μV/mA, and a power consumption of 1.5 μA.

Recently, research on neural light field (NLF), which applies implicit neural representation (INR) to light field (LF), has been actively conducted. NLF can reconstruct dense and realistic LF from relatively sparse and unstructured images, which alleviates the high acquisition difficulty of existing LFs. On the other hand, NLF has a slow rendering speed due to pixel-level MLP processing, making real-time rendering challenging. To address real-time rendering of NLF, this paper considers the application of an explicit voxel grid (VG) data structure, which is used to improve the rendering speed of INR. In particular, the performance is compared based on the dimensions of VG. Experimental results show that the dimensions of VG involve a trade-off between rendering quality, memory usage, and training speed. The analysis presented in this paper is expected to help select the appropriate dimensions of VG according to the specific application scenario.

In pursuit of an efficient and precise method for measuring the Leaf Area Index (LAI), this paper designs and implements a portable LAI measurement instrument based on hemispherical photography, designated as LAI-HP. Constructed upon an embedded platform, this device integrates advanced functionalities of image acquisition, processing, and storage in a single compact unit. Not only does it simplify operational procedures, enabling users to readily master the measurement technique, but it also ensures high accuracy by providing exact analysis of hemispherical canopy images, thereby rapidly and accurately extracting the leaf area index. Comparative experiments reveal a highly significant correlation between the measurement results of LAI-HP and those obtained from the LAI-2200C (R = 0.889, RMSE = 0.441), demonstrating its capability to meet the requirements for LAI measurements in major ecosystems such as farmlands and forests.