A 16-bit SAR ADC featuring bitonic sorting-based capacitor recombination calibration

Abstract

This paper presents a 16-bit, 1-MS/s SAR ADC featuring a bitonic sorting-based capacitor recombination calibration technique. The capacitor recombination calibration exploits inherent device mismatches for mutual compensation, thereby eliminating the need for additional analog circuitry and complex digital computations. By employing a floating-capacitor technique, the calibration algorithm's tolerance to comparator offset voltage and noise is significantly enhanced. Compared to conventional sorting, the adopted bitonic sorting algorithm offers superior time complexity, stronger interference immunity, and reduced hardware overhead. The feasibility of the calibration technique is verified through behavioral-level modeling, and a circuit prototype is implemented in a 180-nm CMOS process. Simulation results demonstrate that the calibration improves the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 85.3 dB and 91.1 dB to 94.1 dB and 108.6 dB, respectively.