A 28 nm 151 KOPS 10 nJ computing-in-memory reconfigurable number theoretic transform accelerator

Abstract

Lattice-based cryptography provides the security foundation for both post-quantum cryptography (PQC) and homomorphic encryption (HE). Number theoretic transforms (NTT) contribute significantly to the latency and energy consumption in cryptographic computations. This work presents a Compute-in-Memory (CIM) reconfigurable NTT accelerator for PQC and HE. The accelerator incorporates a reconfigurable array to minimize data latency, CIM processing elements to reduce memory and power consumption, and a parallel circuit for lattice-based cryptographic protocol deployment. A 28 nm chip of the accelerator consumes only 10 nJ per 256-point NTT, while achieving a throughput of 151.2 KOPS during Kyber-512 that achieves a remarkable reduction of up to 75% in clock cycles and a 70% reduction in energy consumption than the state-of-the-art.