IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Dual-clock MASH delta-sigma modulator employing a frequency modulated intermediate signal
Koichi MaezawaMario SakouWataru MatsubaraTakashi Mizutani
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2006 Volume 3 Issue 21 Pages 459-463

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Abstract

A dual-clock MASH (multi-stage noise shaping) delta-sigma modulator (DSM) is proposed for high performance analog-digital converter. This employs a DSM using a frequency modulated intermediate signal (FMDSM) for the last stage. The sampling clock frequency for the last stage can be increased due to the features of the FMDSM. It is shown that this can increase the SNR beyond the conventional MASH DSMs.

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© 2006 by The Institute of Electronics, Information and Communication Engineers
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