IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 3 , Issue 21
Showing 1-2 articles out of 2 articles from the selected issue
LETTER
  • Masaaki Iijima, Kenji Hamada, Masayuki Kitamura, Masahiro Numa, Akira ...
    2006 Volume 3 Issue 21 Pages 453-458
    Published: 2006
    Released: November 10, 2006
    JOURNALS FREE ACCESS
    The dual supply voltage (dual-VDD) scheme reduces the active power consumption without performance degradation by using two power supply rails. However, an increase in the delay due to the scaled-down supply voltage has made assigning the lower supply voltage (VDDL) more difficult in the conventional dual-VDD scheme. We propose a technique for the dual-VDD scheme employing the Active Body-biasing Control (ABC) on PD-SOI, which increases the number of VDDL-cells owing to lowered threshold voltage. Simulation results have shown our approach effectively reduces the power consumption even at low voltage operation.
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  • Koichi Maezawa, Mario Sakou, Wataru Matsubara, Takashi Mizutani
    2006 Volume 3 Issue 21 Pages 459-463
    Published: 2006
    Released: November 10, 2006
    JOURNALS FREE ACCESS
    A dual-clock MASH (multi-stage noise shaping) delta-sigma modulator (DSM) is proposed for high performance analog-digital converter. This employs a DSM using a frequency modulated intermediate signal (FMDSM) for the last stage. The sampling clock frequency for the last stage can be increased due to the features of the FMDSM. It is shown that this can increase the SNR beyond the conventional MASH DSMs.
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